i2c_timesim.v

在一个32单元CPLD中实现的I2C SLave device

  X_OR2 \state<1>_MC_tsimcreated_prld_  (
    .I0(\FOOBAR1__ctinst/5_102 ),
    .I1(Gnd_15),
    .O(\state<1>_MC_tsimcreated_prld__111 )
  );
  defparam \state<1>_MC.REG .INIT = 1'b0;
  X_FF \state<1>_MC.REG  (
    .I(\state<1>_MC.D_112 ),
    .CE(Vcc_92),
    .CLK(\scl_II/FCLK_17 ),
    .SET(Gnd_15),
    .RST(\state<1>_MC_tsimcreated_prld__111 ),
    .O(\state<1>_MC.Q )
  );
  X_XOR2 \state<1>_MC.D  (
    .I0(\NlwInverterSignal_state<1>_MC.D/IN0 ),
    .I1(\state<1>_MC.D2_114 ),
    .O(\state<1>_MC.D_112 )
  );
  X_ZERO \state<1>_MC.D1  (
    .O(\state<1>_MC.D1_113 )
  );
  X_AND2 \state<1>_MC.D2_PT_0  (
    .I0(state[0]),
    .I1(state[1]),
    .O(\state<1>_MC.D2_PT_0_115 )
  );
  X_AND2 \state<1>_MC.D2_PT_1  (
    .I0(\NlwInverterSignal_state<1>_MC.D2_PT_1/IN0 ),
    .I1(\NlwInverterSignal_state<1>_MC.D2_PT_1/IN1 ),
    .O(\state<1>_MC.D2_PT_1_116 )
  );
  X_AND5 \state<1>_MC.D2_PT_2  (
    .I0(state[0]),
    .I1(\NlwInverterSignal_state<1>_MC.D2_PT_2/IN1 ),
    .I2(\NlwInverterSignal_state<1>_MC.D2_PT_2/IN2 ),
    .I3(\NlwInverterSignal_state<1>_MC.D2_PT_2/IN3 ),
    .I4(\sda_II/UIM_19 ),
    .O(\state<1>_MC.D2_PT_2_117 )
  );
  X_AND5 \state<1>_MC.D2_PT_3  (
    .I0(\NlwInverterSignal_state<1>_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_state<1>_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_state<1>_MC.D2_PT_3/IN2 ),
    .I3(\NlwInverterSignal_state<1>_MC.D2_PT_3/IN3 ),
    .I4(\NlwInverterSignal_state<1>_MC.D2_PT_3/IN4 ),
    .O(\state<1>_MC.D2_PT_3_118 )
  );
  X_OR4 \state<1>_MC.D2  (
    .I0(\state<1>_MC.D2_PT_0_115 ),
    .I1(\state<1>_MC.D2_PT_1_116 ),
    .I2(\state<1>_MC.D2_PT_2_117 ),
    .I3(\state<1>_MC.D2_PT_3_118 ),
    .O(\state<1>_MC.D2_114 )
  );
  X_BUF \state<3>  (
    .I(\state<3>_MC.Q ),
    .O(state[3])
  );
  X_XOR2 \state<3>_MC_tsimcreated_xor_  (
    .I0(\state<3>_MC.D_119 ),
    .I1(\state<3>_MC.Q ),
    .O(\state<3>_MC_tsimcreated_xor__120 )
  );
  X_OR2 \state<3>_MC_tsimcreated_prld_  (
    .I0(\FOOBAR1__ctinst/5_102 ),
    .I1(Gnd_15),
    .O(\state<3>_MC_tsimcreated_prld__121 )
  );
  defparam \state<3>_MC.REG .INIT = 1'b0;
  X_FF \state<3>_MC.REG  (
    .I(\state<3>_MC_tsimcreated_xor__120 ),
    .CE(Vcc_92),
    .CLK(\scl_II/FCLK_17 ),
    .SET(Gnd_15),
    .RST(\state<3>_MC_tsimcreated_prld__121 ),
    .O(\state<3>_MC.Q )
  );
  X_XOR2 \state<3>_MC.D  (
    .I0(\state<3>_MC.D1_122 ),
    .I1(\state<3>_MC.D2_123 ),
    .O(\state<3>_MC.D_119 )
  );
  X_ZERO \state<3>_MC.D1  (
    .O(\state<3>_MC.D1_122 )
  );
  X_AND3 \state<3>_MC.D2_PT_0  (
    .I0(state[0]),
    .I1(state[2]),
    .I2(state[1]),
    .O(\state<3>_MC.D2_PT_0_124 )
  );
  X_AND5 \state<3>_MC.D2_PT_1  (
    .I0(state[0]),
    .I1(state[1]),
    .I2(state[3]),
    .I3(state[4]),
    .I4(\NlwInverterSignal_state<3>_MC.D2_PT_1/IN4 ),
    .O(\state<3>_MC.D2_PT_1_125 )
  );
  X_AND7 \state<3>_MC.D2_PT_2  (
    .I0(\NlwInverterSignal_state<3>_MC.D2_PT_2/IN0 ),
    .I1(state[2]),
    .I2(\NlwInverterSignal_state<3>_MC.D2_PT_2/IN2 ),
    .I3(state[3]),
    .I4(state[4]),
    .I5(\NlwInverterSignal_state<3>_MC.D2_PT_2/IN5 ),
    .I6(\NlwInverterSignal_state<3>_MC.D2_PT_2/IN6 ),
    .O(\state<3>_MC.D2_PT_2_126 )
  );
  X_AND7 \state<3>_MC.D2_PT_3  (
    .I0(\NlwInverterSignal_state<3>_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_state<3>_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_state<3>_MC.D2_PT_3/IN2 ),
    .I3(state[3]),
    .I4(\NlwInverterSignal_state<3>_MC.D2_PT_3/IN4 ),
    .I5(\NlwInverterSignal_state<3>_MC.D2_PT_3/IN5 ),
    .I6(\sda_II/UIM_19 ),
    .O(\state<3>_MC.D2_PT_3_127 )
  );
  X_OR4 \state<3>_MC.D2  (
    .I0(\state<3>_MC.D2_PT_0_124 ),
    .I1(\state<3>_MC.D2_PT_1_125 ),
    .I2(\state<3>_MC.D2_PT_2_126 ),
    .I3(\state<3>_MC.D2_PT_3_127 ),
    .O(\state<3>_MC.D2_123 )
  );
  X_BUF \state<4>  (
    .I(\state<4>_MC.Q ),
    .O(state[4])
  );
  X_XOR2 \state<4>_MC_tsimcreated_xor_  (
    .I0(\state<4>_MC.D_128 ),
    .I1(\state<4>_MC.Q ),
    .O(\state<4>_MC_tsimcreated_xor__129 )
  );
  X_OR2 \state<4>_MC_tsimcreated_prld_  (
    .I0(\FOOBAR1__ctinst/5_102 ),
    .I1(Gnd_15),
    .O(\state<4>_MC_tsimcreated_prld__130 )
  );
  defparam \state<4>_MC.REG .INIT = 1'b0;
  X_FF \state<4>_MC.REG  (
    .I(\state<4>_MC_tsimcreated_xor__129 ),
    .CE(Vcc_92),
    .CLK(\scl_II/FCLK_17 ),
    .SET(Gnd_15),
    .RST(\state<4>_MC_tsimcreated_prld__130 ),
    .O(\state<4>_MC.Q )
  );
  X_XOR2 \state<4>_MC.D  (
    .I0(\state<4>_MC.D1_131 ),
    .I1(\state<4>_MC.D2_132 ),
    .O(\state<4>_MC.D_128 )
  );
  X_ZERO \state<4>_MC.D1  (
    .O(\state<4>_MC.D1_131 )
  );
  X_AND5 \state<4>_MC.D2_PT_0  (
    .I0(state[0]),
    .I1(state[2]),
    .I2(state[1]),
    .I3(state[3]),
    .I4(state[4]),
    .O(\state<4>_MC.D2_PT_0_133 )
  );
  X_AND5 \state<4>_MC.D2_PT_1  (
    .I0(state[0]),
    .I1(state[2]),
    .I2(state[1]),
    .I3(state[3]),
    .I4(\NlwInverterSignal_state<4>_MC.D2_PT_1/IN4 ),
    .O(\state<4>_MC.D2_PT_1_134 )
  );
  X_AND5 \state<4>_MC.D2_PT_2  (
    .I0(state[0]),
    .I1(state[1]),
    .I2(state[3]),
    .I3(state[4]),
    .I4(\NlwInverterSignal_state<4>_MC.D2_PT_2/IN4 ),
    .O(\state<4>_MC.D2_PT_2_135 )
  );
  X_AND6 \state<4>_MC.D2_PT_3  (
    .I0(state[0]),
    .I1(state[2]),
    .I2(state[1]),
    .I3(\NlwInverterSignal_state<4>_MC.D2_PT_3/IN3 ),
    .I4(\NlwInverterSignal_state<4>_MC.D2_PT_3/IN4 ),
    .I5(\NlwInverterSignal_state<4>_MC.D2_PT_3/IN5 ),
    .O(\state<4>_MC.D2_PT_3_136 )
  );
  X_AND7 \state<4>_MC.D2_PT_4  (
    .I0(\NlwInverterSignal_state<4>_MC.D2_PT_4/IN0 ),
    .I1(state[2]),
    .I2(\NlwInverterSignal_state<4>_MC.D2_PT_4/IN2 ),
    .I3(state[3]),
    .I4(state[4]),
    .I5(\NlwInverterSignal_state<4>_MC.D2_PT_4/IN5 ),
    .I6(\NlwInverterSignal_state<4>_MC.D2_PT_4/IN6 ),
    .O(\state<4>_MC.D2_PT_4_137 )
  );
  X_OR5 \state<4>_MC.D2  (
    .I0(\state<4>_MC.D2_PT_0_133 ),
    .I1(\state<4>_MC.D2_PT_1_134 ),
    .I2(\state<4>_MC.D2_PT_2_135 ),
    .I3(\state<4>_MC.D2_PT_3_136 ),
    .I4(\state<4>_MC.D2_PT_4_137 ),
    .O(\state<4>_MC.D2_132 )
  );
  X_BUF \state<5>  (
    .I(\state<5>_MC.Q ),
    .O(state[5])
  );
  X_XOR2 \state<5>_MC_tsimcreated_xor_  (
    .I0(\state<5>_MC.D_138 ),
    .I1(\state<5>_MC.Q ),
    .O(\state<5>_MC_tsimcreated_xor__139 )
  );
  X_OR2 \state<5>_MC_tsimcreated_prld_  (
    .I0(\FOOBAR1__ctinst/5_102 ),
    .I1(Gnd_15),
    .O(\state<5>_MC_tsimcreated_prld__140 )
  );
  defparam \state<5>_MC.REG .INIT = 1'b0;
  X_FF \state<5>_MC.REG  (
    .I(\state<5>_MC_tsimcreated_xor__139 ),
    .CE(Vcc_92),
    .CLK(\scl_II/FCLK_17 ),
    .SET(Gnd_15),
    .RST(\state<5>_MC_tsimcreated_prld__140 ),
    .O(\state<5>_MC.Q )
  );
  X_XOR2 \state<5>_MC.D  (
    .I0(\state<5>_MC.D1_141 ),
    .I1(\state<5>_MC.D2_142 ),
    .O(\state<5>_MC.D_138 )
  );
  X_ZERO \state<5>_MC.D1  (
    .O(\state<5>_MC.D1_141 )
  );
  X_AND5 \state<5>_MC.D2_PT_0  (
    .I0(state[0]),
    .I1(state[2]),
    .I2(state[1]),
    .I3(state[3]),
    .I4(state[4]),
    .O(\state<5>_MC.D2_PT_0_143 )
  );
  X_AND5 \state<5>_MC.D2_PT_1  (
    .I0(state[0]),
    .I1(state[2]),
    .I2(state[1]),
    .I3(state[3]),
    .I4(state[5]),
    .O(\state<5>_MC.D2_PT_1_144 )
  );
  X_OR2 \state<5>_MC.D2  (
    .I0(\state<5>_MC.D2_PT_0_143 ),
    .I1(\state<5>_MC.D2_PT_1_144 ),
    .O(\state<5>_MC.D2_142 )
  );
  X_BUF N_PZ_227 (
    .I(\N_PZ_227_MC.Q_145 ),
    .O(N_PZ_227_146)
  );
  X_BUF \N_PZ_227_MC.Q  (
    .I(\N_PZ_227_MC.D_147 ),
    .O(\N_PZ_227_MC.Q_145 )
  );
  X_XOR2 \N_PZ_227_MC.D  (
    .I0(\N_PZ_227_MC.D1_148 ),
    .I1(\N_PZ_227_MC.D2_149 ),
    .O(\N_PZ_227_MC.D_147 )
  );
  X_AND2 \N_PZ_227_MC.D1  (
    .I0(\clr_n_II/UIM_3 ),
    .I1(\NlwInverterSignal_N_PZ_227_MC.D1/IN1 ),
    .O(\N_PZ_227_MC.D1_148 )
  );
  X_ZERO \N_PZ_227_MC.D2  (
    .O(\N_PZ_227_MC.D2_149 )
  );
  X_BUF start (
    .I(\start_MC.Q ),
    .O(start_150)
  );
  X_OR2 start_MC_tsimcreated_prld_ (
    .I0(\FOOBAR2__ctinst/5_151 ),
    .I1(Gnd_15),
    .O(start_MC_tsimcreated_prld__152)
  );
  defparam \start_MC.REG .INIT = 1'b0;
  X_FF \start_MC.REG  (
    .I(\start_MC.D_153 ),
    .CE(Vcc_92),
    .CLK(\start_MC.REG_tsimcreated_inv_sda_II/FCLK_154 ),
    .SET(Gnd_15),
    .RST(start_MC_tsimcreated_prld__152),
    .O(\start_MC.Q )
  );
  X_INV \start_MC.REG_tsimcreated_inv_sda_II/FCLK  (
    .I(\sda_II/FCLK_20 ),
    .O(\start_MC.REG_tsimcreated_inv_sda_II/FCLK_154 )
  );
  X_XOR2 \start_MC.D  (
    .I0(\NlwInverterSignal_start_MC.D/IN0 ),
    .I1(\start_MC.D2_156 ),
    .O(\start_MC.D_153 )
  );
  X_ZERO \start_MC.D1  (
    .O(\start_MC.D1_155 )
  );
  X_ZERO \start_MC.D2  (
    .O(\start_MC.D2_156 )
  );
  X_BUF N_PZ_222 (
    .I(\N_PZ_222_MC.Q_157 ),
    .O(N_PZ_222_158)
  );
  X_BUF \N_PZ_222_MC.Q  (
    .I(\N_PZ_222_MC.D_159 ),
    .O(\N_PZ_222_MC.Q_157 )
  );
  X_XOR2 \N_PZ_222_MC.D  (
    .I0(\N_PZ_222_MC.D1_160 ),
    .I1(\N_PZ_222_MC.D2_161 ),
    .O(\N_PZ_222_MC.D_159 )
  );
  X_AND2 \N_PZ_222_MC.D1  (
    .I0(\clr_n_II/UIM_3 ),
    .I1(\scl_II/UIM_21 ),
    .O(\N_PZ_222_MC.D1_160 )
  );
  X_ZERO \N_PZ_222_MC.D2  (
    .O(\N_PZ_222_MC.D2_161 )
  );
  X_AND6 \inport_pre<1>_MC.CE  (
    .I0(state[0]),
    .I1(state[2]),
    .I2(\NlwInverterSignal_inport_pre<1>_MC.CE/IN2 ),
    .I3(state[3]),
    .I4(state[4]),
    .I5(\NlwInverterSignal_inport_pre<1>_MC.CE/IN5 ),
    .O(\inport_pre<1>_MC.CE_25 )
  );
  X_AND6 \inport_pre<3>_MC.CE  (
    .I0(state[0]),
    .I1(state[2]),
    .I2(\NlwInverterSignal_inport_pre<3>_MC.CE/IN2 ),
    .I3(state[3]),
    .I4(state[4]),
    .I5(\NlwInverterSignal_inport_pre<3>_MC.CE/IN5 ),
    .O(\inport_pre<3>_MC.CE_29 )
  );
  X_AND6 \inport_pre<4>_MC.CE  (
    .I0(state[0]),
    .I1(state[2]),
    .I2(\NlwInverterSignal_inport_pre<4>_MC.CE/IN2 ),
    .I3(state[3]),
    .I4(state[4]),
    .I5(\NlwInverterSignal_inport_pre<4>_MC.CE/IN5 ),
    .O(\inport_pre<4>_MC.CE_33 )
  );
  X_AND6 \inport_pre<5>_MC.CE  (
    .I0(state[0]),
    .I1(state[2]),
    .I2(\NlwInverterSignal_inport_pre<5>_MC.CE/IN2 ),
    .I3(state[3]),
    .I4(state[4]),
    .I5(\NlwInverterSignal_inport_pre<5>_MC.CE/IN5 ),
    .O(\inport_pre<5>_MC.CE_37 )
  );
  X_AND6 \inport_pre<6>_MC.CE  (
    .I0(state[0]),
    .I1(state[2]),
    .I2(\NlwInverterSignal_inport_pre<6>_MC.CE/IN2 ),
    .I3(state[3]),
    .I4(state[4]),
    .I5(\NlwInverterSignal_inport_pre<6>_MC.CE/IN5 ),
    .O(\inport_pre<6>_MC.CE_41 )
  );
  X_AND6 \inport_pre<7>_MC.CE  (
    .I0(state[0]),
    .I1(state[2]),
    .I2(\NlwInverterSignal_inport_pre<7>_MC.CE/IN2 ),
    .I3(state[3]),
    .I4(state[4]),
    .I5(\NlwInverterSignal_inport_pre<7>_MC.CE/IN5 ),
    .O(\inport_pre<7>_MC.CE_45 )
  );
  X_AND6 \inport_pre<8>_MC.CE  (
    .I0(state[0]),
    .I1(state[2]),
    .I2(\NlwInverterSignal_inport_pre<8>_MC.CE/IN2 ),
    .I3(state[3]),
    .I4(state[4]),
    .I5(\NlwInverterSignal_inport_pre<8>_MC.CE/IN5 ),
    .O(\inport_pre<8>_MC.CE_49 )
  );
  X_BUF \inport_pre<9>  (
    .I(\inport_pre<9>_MC.Q ),
    .O(inport_pre[9])
  );
  X_XOR2 \inport_pre<9>_MC_tsimcreated_xor_  (
    .I0(\inport_pre<9>_MC.D_162 ),
    .I1(\inport_pre<9>_MC.Q ),
    .O(\inport_pre<9>_MC_tsimcreated_xor__163 )
  );
  X_OR2 \inport_pre<9>_MC_tsimcreated_prld_  (
    .I0(\clr_n_II/FSR-_4 ),
    .I1(Gnd_15),
    .O(\inport_pre<9>_MC_tsimcreated_prld__164 )
  );
  defparam \inport_pre<9>_MC.REG .INIT = 1'b0;
  X_FF \inport_pre<9>_MC.REG  (
    .I(\inport_pre<9>_MC_tsimcreated_xor__163 ),
    .CE(Vcc_92),
    .CLK(\scl_II/FCLK_17 ),
    .SET(Gnd_15),
    .RST(\inport_pre<9>_MC_tsimcreated_prld__164 ),
    .O(\inport_pre<9>_MC.Q )
  );
  X_XOR2 \inport_pre<9>_MC.D  (
    .I0(\inport_pre<9>_MC.D1_165 ),
    .I1(\inport_pre<9>_MC.D2_166 ),
    .O(\inport_pre<9>_MC.D_162 )
  );
  X_ZERO \inport_pre<9>_MC.D1  (