i2c_timesim.v

来自「在一个32单元CPLD中实现的I2C SLave device」· Verilog 代码 · 共 2,136 行 · 第 1/5 页

    .O(\scl_int_II/FCLK_50 )
  );
  X_OPAD \outport.PAD  (
    .PAD(outport)
  );
  X_TRI outport_0 (
    .I(Gnd_15),
    .CTL(\NlwInverterSignal_outport/CTL ),
    .O(outport)
  );
  X_OPAD \portsel<0>.PAD  (
    .PAD(portsel[0])
  );
  X_BUF \portsel<0>  (
    .I(\portsel<0>_MC.Q_52 ),
    .O(portsel[0])
  );
  X_OPAD \portsel<1>.PAD  (
    .PAD(portsel[1])
  );
  X_BUF \portsel<1>  (
    .I(\portsel<1>_MC.Q_53 ),
    .O(portsel[1])
  );
  X_OPAD \portsel<2>.PAD  (
    .PAD(portsel[2])
  );
  X_BUF \portsel<2>  (
    .I(\portsel<2>_MC.Q_54 ),
    .O(portsel[2])
  );
  X_OPAD \portsel<3>.PAD  (
    .PAD(portsel[3])
  );
  X_BUF \portsel<3>  (
    .I(\portsel<3>_MC.Q_55 ),
    .O(portsel[3])
  );
  X_OPAD \portsel<4>.PAD  (
    .PAD(portsel[4])
  );
  X_BUF \portsel<4>  (
    .I(\portsel<4>_MC.Q_56 ),
    .O(portsel[4])
  );
  X_OPAD \portsel<5>.PAD  (
    .PAD(portsel[5])
  );
  X_BUF \portsel<5>  (
    .I(\portsel<5>_MC.Q_57 ),
    .O(portsel[5])
  );
  X_OPAD \portsel<6>.PAD  (
    .PAD(portsel[6])
  );
  X_BUF \portsel<6>  (
    .I(\portsel<6>_MC.Q_58 ),
    .O(portsel[6])
  );
  X_OPAD \portsel<7>.PAD  (
    .PAD(portsel[7])
  );
  X_BUF \portsel<7>  (
    .I(\portsel<7>_MC.Q_59 ),
    .O(portsel[7])
  );
  X_OPAD \scl_n.PAD  (
    .PAD(scl_n)
  );
  X_TRI scl_n_1 (
    .I(Gnd_15),
    .CTL(\NlwInverterSignal_scl_n/CTL ),
    .O(scl_n)
  );
  X_BPAD \sda.PAD  (
    .PAD(sda)
  );
  X_TRI sda_2 (
    .I(Gnd_15),
    .CTL(\NlwInverterSignal_sda/CTL ),
    .O(sda)
  );
  X_BUF \outport_MC.Q  (
    .I(\outport_MC.Q_tsimrenamed_net__62 ),
    .O(\outport_MC.Q_51 )
  );
  X_BUF \outport_MC.Q_tsimrenamed_net_  (
    .I(\outport_MC.D_63 ),
    .O(\outport_MC.Q_tsimrenamed_net__62 )
  );
  X_XOR2 \outport_MC.D  (
    .I0(\NlwInverterSignal_outport_MC.D/IN0 ),
    .I1(\outport_MC.D2_65 ),
    .O(\outport_MC.D_63 )
  );
  X_ZERO \outport_MC.D1  (
    .O(\outport_MC.D1_64 )
  );
  X_AND2 \outport_MC.D2_PT_0  (
    .I0(N_PZ_186_66),
    .I1(N_PZ_186_66),
    .O(\outport_MC.D2_PT_0_67 )
  );
  X_AND2 \outport_MC.D2_PT_1  (
    .I0(\inport<14>_II/UIM_7 ),
    .I1(\NlwInverterSignal_outport_MC.D2_PT_1/IN1 ),
    .O(\outport_MC.D2_PT_1_68 )
  );
  X_AND2 \outport_MC.D2_PT_2  (
    .I0(\inport<15>_II/UIM_8 ),
    .I1(\NlwInverterSignal_outport_MC.D2_PT_2/IN1 ),
    .O(\outport_MC.D2_PT_2_69 )
  );
  X_AND2 \outport_MC.D2_PT_3  (
    .I0(\inport<0>_II/UIM_13 ),
    .I1(\NlwInverterSignal_outport_MC.D2_PT_3/IN1 ),
    .O(\outport_MC.D2_PT_3_70 )
  );
  X_AND2 \outport_MC.D2_PT_4  (
    .I0(\NlwInverterSignal_outport_MC.D2_PT_4/IN0 ),
    .I1(inport_pre[0]),
    .O(\outport_MC.D2_PT_4_71 )
  );
  X_AND2 \outport_MC.D2_PT_5  (
    .I0(\inport<1>_II/UIM_22 ),
    .I1(\NlwInverterSignal_outport_MC.D2_PT_5/IN1 ),
    .O(\outport_MC.D2_PT_5_72 )
  );
  X_AND2 \outport_MC.D2_PT_6  (
    .I0(\NlwInverterSignal_outport_MC.D2_PT_6/IN0 ),
    .I1(inport_pre[1]),
    .O(\outport_MC.D2_PT_6_73 )
  );
  X_AND2 \outport_MC.D2_PT_7  (
    .I0(\inport<3>_II/UIM_26 ),
    .I1(\NlwInverterSignal_outport_MC.D2_PT_7/IN1 ),
    .O(\outport_MC.D2_PT_7_74 )
  );
  X_AND2 \outport_MC.D2_PT_8  (
    .I0(\NlwInverterSignal_outport_MC.D2_PT_8/IN0 ),
    .I1(inport_pre[3]),
    .O(\outport_MC.D2_PT_8_75 )
  );
  X_AND2 \outport_MC.D2_PT_9  (
    .I0(\inport<4>_II/UIM_30 ),
    .I1(\NlwInverterSignal_outport_MC.D2_PT_9/IN1 ),
    .O(\outport_MC.D2_PT_9_76 )
  );
  X_AND2 \outport_MC.D2_PT_10  (
    .I0(\NlwInverterSignal_outport_MC.D2_PT_10/IN0 ),
    .I1(inport_pre[4]),
    .O(\outport_MC.D2_PT_10_77 )
  );
  X_AND2 \outport_MC.D2_PT_11  (
    .I0(\inport<5>_II/UIM_34 ),
    .I1(\NlwInverterSignal_outport_MC.D2_PT_11/IN1 ),
    .O(\outport_MC.D2_PT_11_78 )
  );
  X_AND2 \outport_MC.D2_PT_12  (
    .I0(\NlwInverterSignal_outport_MC.D2_PT_12/IN0 ),
    .I1(inport_pre[5]),
    .O(\outport_MC.D2_PT_12_79 )
  );
  X_AND2 \outport_MC.D2_PT_13  (
    .I0(\inport<6>_II/UIM_38 ),
    .I1(\NlwInverterSignal_outport_MC.D2_PT_13/IN1 ),
    .O(\outport_MC.D2_PT_13_80 )
  );
  X_AND2 \outport_MC.D2_PT_14  (
    .I0(\NlwInverterSignal_outport_MC.D2_PT_14/IN0 ),
    .I1(inport_pre[6]),
    .O(\outport_MC.D2_PT_14_81 )
  );
  X_AND2 \outport_MC.D2_PT_15  (
    .I0(\inport<12>_II/UIM_42 ),
    .I1(\NlwInverterSignal_outport_MC.D2_PT_15/IN1 ),
    .O(\outport_MC.D2_PT_15_82 )
  );
  X_AND2 \outport_MC.D2_PT_16  (
    .I0(\NlwInverterSignal_outport_MC.D2_PT_16/IN0 ),
    .I1(inport_pre[7]),
    .O(\outport_MC.D2_PT_16_83 )
  );
  X_AND2 \outport_MC.D2_PT_17  (
    .I0(\inport<13>_II/UIM_46 ),
    .I1(\NlwInverterSignal_outport_MC.D2_PT_17/IN1 ),
    .O(\outport_MC.D2_PT_17_84 )
  );
  X_AND2 \outport_MC.D2_PT_18  (
    .I0(\NlwInverterSignal_outport_MC.D2_PT_18/IN0 ),
    .I1(inport_pre[8]),
    .O(\outport_MC.D2_PT_18_85 )
  );
  X_AND3 \outport_MC.D2_PT_19  (
    .I0(\NlwInverterSignal_outport_MC.D2_PT_19/IN0 ),
    .I1(\NlwInverterSignal_outport_MC.D2_PT_19/IN1 ),
    .I2(inport_pre[9]),
    .O(\outport_MC.D2_PT_19_86 )
  );
  X_OR32 \outport_MC.D2  (
    .I0(\outport_MC.D2_PT_0_67 ),
    .I1(\outport_MC.D2_PT_1_68 ),
    .I2(\outport_MC.D2_PT_2_69 ),
    .I3(\outport_MC.D2_PT_3_70 ),
    .I4(\outport_MC.D2_PT_4_71 ),
    .I5(\outport_MC.D2_PT_5_72 ),
    .I6(\outport_MC.D2_PT_6_73 ),
    .I7(\outport_MC.D2_PT_7_74 ),
    .I8(\outport_MC.D2_PT_8_75 ),
    .I9(\outport_MC.D2_PT_9_76 ),
    .I10(\outport_MC.D2_PT_10_77 ),
    .I11(\outport_MC.D2_PT_11_78 ),
    .I12(\outport_MC.D2_PT_12_79 ),
    .I13(\outport_MC.D2_PT_13_80 ),
    .I14(\outport_MC.D2_PT_14_81 ),
    .I15(\outport_MC.D2_PT_15_82 ),
    .I16(\outport_MC.D2_PT_16_83 ),
    .I17(\outport_MC.D2_PT_17_84 ),
    .I18(\outport_MC.D2_PT_18_85 ),
    .I19(\outport_MC.D2_PT_19_86 ),
    .I20(Gnd_15),
    .I21(Gnd_15),
    .I22(Gnd_15),
    .I23(Gnd_15),
    .I24(Gnd_15),
    .I25(Gnd_15),
    .I26(Gnd_15),
    .I27(Gnd_15),
    .I28(Gnd_15),
    .I29(Gnd_15),
    .I30(Gnd_15),
    .I31(Gnd_15),
    .O(\outport_MC.D2_65 )
  );
  X_AND6 \inport_pre<0>_MC.CE  (
    .I0(state[0]),
    .I1(state[2]),
    .I2(\NlwInverterSignal_inport_pre<0>_MC.CE/IN2 ),
    .I3(state[3]),
    .I4(state[4]),
    .I5(\NlwInverterSignal_inport_pre<0>_MC.CE/IN5 ),
    .O(\inport_pre<0>_MC.CE_18 )
  );
  X_BUF \state<0>  (
    .I(\state<0>_MC.Q ),
    .O(state[0])
  );
  X_XOR2 \state<0>_MC_tsimcreated_xor_  (
    .I0(\state<0>_MC.D_87 ),
    .I1(\state<0>_MC.Q ),
    .O(\state<0>_MC_tsimcreated_xor__88 )
  );
  X_AND2 \state<0>_MC_tsimcreated_set_and_noreset_  (
    .I0(\NlwInverterSignal_state<0>_MC_tsimcreated_set_and_noreset_/IN0 ),
    .I1(\FOOBAR1__ctinst/6_89 ),
    .O(\state<0>_MC_tsimcreated_set_and_noreset__90 )
  );
  X_OR2 \state<0>_MC_tsimcreated_prld_  (
    .I0(\clr_n_II/FSR-_4 ),
    .I1(Gnd_15),
    .O(\state<0>_MC_tsimcreated_prld__91 )
  );
  defparam \state<0>_MC.REG .INIT = 1'b0;
  X_FF \state<0>_MC.REG  (
    .I(\state<0>_MC_tsimcreated_xor__88 ),
    .CE(Vcc_92),
    .CLK(\scl_II/FCLK_17 ),
    .SET(\state<0>_MC_tsimcreated_set_and_noreset__90 ),
    .RST(\state<0>_MC_tsimcreated_prld__91 ),
    .O(\state<0>_MC.Q )
  );
  X_ONE Vcc (
    .O(Vcc_92)
  );
  X_XOR2 \state<0>_MC.D  (
    .I0(\NlwInverterSignal_state<0>_MC.D/IN0 ),
    .I1(\state<0>_MC.D2_94 ),
    .O(\state<0>_MC.D_87 )
  );
  X_ZERO \state<0>_MC.D1  (
    .O(\state<0>_MC.D1_93 )
  );
  X_AND6 \state<0>_MC.D2_PT_0  (
    .I0(\NlwInverterSignal_state<0>_MC.D2_PT_0/IN0 ),
    .I1(\NlwInverterSignal_state<0>_MC.D2_PT_0/IN1 ),
    .I2(\NlwInverterSignal_state<0>_MC.D2_PT_0/IN2 ),
    .I3(\NlwInverterSignal_state<0>_MC.D2_PT_0/IN3 ),
    .I4(\NlwInverterSignal_state<0>_MC.D2_PT_0/IN4 ),
    .I5(\sda_II/UIM_19 ),
    .O(\state<0>_MC.D2_PT_0_95 )
  );
  X_AND6 \state<0>_MC.D2_PT_1  (
    .I0(\NlwInverterSignal_state<0>_MC.D2_PT_1/IN0 ),
    .I1(\NlwInverterSignal_state<0>_MC.D2_PT_1/IN1 ),
    .I2(\NlwInverterSignal_state<0>_MC.D2_PT_1/IN2 ),
    .I3(\NlwInverterSignal_state<0>_MC.D2_PT_1/IN3 ),
    .I4(\NlwInverterSignal_state<0>_MC.D2_PT_1/IN4 ),
    .I5(\NlwInverterSignal_state<0>_MC.D2_PT_1/IN5 ),
    .O(\state<0>_MC.D2_PT_1_96 )
  );
  X_AND6 \state<0>_MC.D2_PT_2  (
    .I0(\NlwInverterSignal_state<0>_MC.D2_PT_2/IN0 ),
    .I1(state[1]),
    .I2(\NlwInverterSignal_state<0>_MC.D2_PT_2/IN2 ),
    .I3(\NlwInverterSignal_state<0>_MC.D2_PT_2/IN3 ),
    .I4(\NlwInverterSignal_state<0>_MC.D2_PT_2/IN4 ),
    .I5(\NlwInverterSignal_state<0>_MC.D2_PT_2/IN5 ),
    .O(\state<0>_MC.D2_PT_2_97 )
  );
  X_AND6 \state<0>_MC.D2_PT_3  (
    .I0(\NlwInverterSignal_state<0>_MC.D2_PT_3/IN0 ),
    .I1(\NlwInverterSignal_state<0>_MC.D2_PT_3/IN1 ),
    .I2(\NlwInverterSignal_state<0>_MC.D2_PT_3/IN2 ),
    .I3(\NlwInverterSignal_state<0>_MC.D2_PT_3/IN3 ),
    .I4(\NlwInverterSignal_state<0>_MC.D2_PT_3/IN4 ),
    .I5(\sda_II/UIM_19 ),
    .O(\state<0>_MC.D2_PT_3_98 )
  );
  X_AND7 \state<0>_MC.D2_PT_4  (
    .I0(\NlwInverterSignal_state<0>_MC.D2_PT_4/IN0 ),
    .I1(state[2]),
    .I2(\NlwInverterSignal_state<0>_MC.D2_PT_4/IN2 ),
    .I3(state[3]),
    .I4(state[4]),
    .I5(\NlwInverterSignal_state<0>_MC.D2_PT_4/IN5 ),
    .I6(\NlwInverterSignal_state<0>_MC.D2_PT_4/IN6 ),
    .O(\state<0>_MC.D2_PT_4_99 )
  );
  X_OR5 \state<0>_MC.D2  (
    .I0(\state<0>_MC.D2_PT_0_95 ),
    .I1(\state<0>_MC.D2_PT_1_96 ),
    .I2(\state<0>_MC.D2_PT_2_97 ),
    .I3(\state<0>_MC.D2_PT_3_98 ),
    .I4(\state<0>_MC.D2_PT_4_99 ),
    .O(\state<0>_MC.D2_94 )
  );
  X_BUF \state<2>  (
    .I(\state<2>_MC.Q ),
    .O(state[2])
  );
  X_XOR2 \state<2>_MC_tsimcreated_xor_  (
    .I0(\state<2>_MC.D_100 ),
    .I1(\state<2>_MC.Q ),
    .O(\state<2>_MC_tsimcreated_xor__101 )
  );
  X_OR2 \state<2>_MC_tsimcreated_prld_  (
    .I0(\FOOBAR1__ctinst/5_102 ),
    .I1(Gnd_15),
    .O(\state<2>_MC_tsimcreated_prld__103 )
  );
  defparam \state<2>_MC.REG .INIT = 1'b0;
  X_FF \state<2>_MC.REG  (
    .I(\state<2>_MC_tsimcreated_xor__101 ),
    .CE(Vcc_92),
    .CLK(\scl_II/FCLK_17 ),
    .SET(Gnd_15),
    .RST(\state<2>_MC_tsimcreated_prld__103 ),
    .O(\state<2>_MC.Q )
  );
  X_XOR2 \state<2>_MC.D  (
    .I0(\state<2>_MC.D1_104 ),
    .I1(\state<2>_MC.D2_105 ),
    .O(\state<2>_MC.D_100 )
  );
  X_AND2 \state<2>_MC.D1  (
    .I0(state[0]),
    .I1(state[1]),
    .O(\state<2>_MC.D1_104 )
  );
  X_AND6 \state<2>_MC.D2_PT_0  (
    .I0(state[0]),
    .I1(\NlwInverterSignal_state<2>_MC.D2_PT_0/IN1 ),
    .I2(state[1]),
    .I3(state[3]),
    .I4(state[4]),
    .I5(\NlwInverterSignal_state<2>_MC.D2_PT_0/IN5 ),
    .O(\state<2>_MC.D2_PT_0_106 )
  );
  X_AND6 \state<2>_MC.D2_PT_1  (
    .I0(state[2]),
    .I1(state[1]),
    .I2(\NlwInverterSignal_state<2>_MC.D2_PT_1/IN2 ),
    .I3(\NlwInverterSignal_state<2>_MC.D2_PT_1/IN3 ),
    .I4(\NlwInverterSignal_state<2>_MC.D2_PT_1/IN4 ),
    .I5(\NlwInverterSignal_state<2>_MC.D2_PT_1/IN5 ),
    .O(\state<2>_MC.D2_PT_1_107 )
  );
  X_AND6 \state<2>_MC.D2_PT_2  (
    .I0(state[2]),
    .I1(\NlwInverterSignal_state<2>_MC.D2_PT_2/IN1 ),
    .I2(\NlwInverterSignal_state<2>_MC.D2_PT_2/IN2 ),
    .I3(\NlwInverterSignal_state<2>_MC.D2_PT_2/IN3 ),
    .I4(\NlwInverterSignal_state<2>_MC.D2_PT_2/IN4 ),
    .I5(\sda_II/UIM_19 ),
    .O(\state<2>_MC.D2_PT_2_108 )
  );
  X_AND7 \state<2>_MC.D2_PT_3  (
    .I0(state[0]),
    .I1(\NlwInverterSignal_state<2>_MC.D2_PT_3/IN1 ),
    .I2(state[1]),
    .I3(\NlwInverterSignal_state<2>_MC.D2_PT_3/IN3 ),
    .I4(\NlwInverterSignal_state<2>_MC.D2_PT_3/IN4 ),
    .I5(\NlwInverterSignal_state<2>_MC.D2_PT_3/IN5 ),
    .I6(\sda_II/UIM_19 ),
    .O(\state<2>_MC.D2_PT_3_109 )
  );
  X_AND7 \state<2>_MC.D2_PT_4  (
    .I0(\NlwInverterSignal_state<2>_MC.D2_PT_4/IN0 ),
    .I1(state[2]),
    .I2(\NlwInverterSignal_state<2>_MC.D2_PT_4/IN2 ),
    .I3(state[3]),
    .I4(state[4]),
    .I5(\NlwInverterSignal_state<2>_MC.D2_PT_4/IN5 ),
    .I6(\NlwInverterSignal_state<2>_MC.D2_PT_4/IN6 ),
    .O(\state<2>_MC.D2_PT_4_110 )
  );
  X_OR5 \state<2>_MC.D2  (
    .I0(\state<2>_MC.D2_PT_0_106 ),
    .I1(\state<2>_MC.D2_PT_1_107 ),
    .I2(\state<2>_MC.D2_PT_2_108 ),
    .I3(\state<2>_MC.D2_PT_3_109 ),
    .I4(\state<2>_MC.D2_PT_4_110 ),
    .O(\state<2>_MC.D2_105 )
  );
  X_BUF \state<1>  (
    .I(\state<1>_MC.Q ),
    .O(state[1])
  );