i2c_timesim.v

来自「在一个32单元CPLD中实现的I2C SLave device」· Verilog 代码 · 共 2,136 行 · 第 1/5 页

  wire \NlwInverterSignal_inport_pre<9>_MC.D2_PT_0/IN4 ;
  wire \NlwInverterSignal_inport_pre<9>_MC.D2_PT_0/IN7 ;
  wire \NlwInverterSignal_inport_pre<9>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_inport_pre<9>_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_inport_pre<9>_MC.D2_PT_1/IN7 ;
  wire \NlwInverterSignal_inport_pre<9>_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_inport_pre<9>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_inport_pre<9>_MC.D2_PT_2/IN5 ;
  wire \NlwInverterSignal_inport_pre<9>_MC.D2_PT_2/IN8 ;
  wire \NlwInverterSignal_N_PZ_186_MC.D1/IN0 ;
  wire \NlwInverterSignal_N_PZ_186_MC.D1/IN1 ;
  wire \NlwInverterSignal_N_PZ_186_MC.D2/IN0 ;
  wire \NlwInverterSignal_N_PZ_186_MC.D2/IN1 ;
  wire \NlwInverterSignal_N_PZ_186_MC.D2/IN2 ;
  wire \NlwInverterSignal_N_PZ_186_MC.D2/IN3 ;
  wire \NlwInverterSignal_N_PZ_186_MC.D2/IN4 ;
  wire \NlwInverterSignal_N_PZ_186_MC.D2/IN5 ;
  wire \NlwInverterSignal_inport_pre<2>_MC.D1/IN3 ;
  wire \NlwInverterSignal_inport_pre<2>_MC.D1/IN6 ;
  wire \NlwInverterSignal_portsel<0>_MC.CE/IN1 ;
  wire \NlwInverterSignal_portsel<0>_MC.CE/IN2 ;
  wire \NlwInverterSignal_portsel<0>_MC.CE/IN3 ;
  wire \NlwInverterSignal_portsel<0>_MC.CE/IN5 ;
  wire \NlwInverterSignal_portsel<1>_MC.CE/IN0 ;
  wire \NlwInverterSignal_portsel<1>_MC.CE/IN1 ;
  wire \NlwInverterSignal_portsel<1>_MC.CE/IN2 ;
  wire \NlwInverterSignal_portsel<1>_MC.CE/IN3 ;
  wire \NlwInverterSignal_portsel<1>_MC.CE/IN5 ;
  wire \NlwInverterSignal_portsel<2>_MC.CE/IN4 ;
  wire \NlwInverterSignal_portsel<2>_MC.CE/IN5 ;
  wire \NlwInverterSignal_portsel<3>_MC.CE/IN0 ;
  wire \NlwInverterSignal_portsel<3>_MC.CE/IN4 ;
  wire \NlwInverterSignal_portsel<3>_MC.CE/IN5 ;
  wire \NlwInverterSignal_portsel<4>_MC.CE/IN2 ;
  wire \NlwInverterSignal_portsel<4>_MC.CE/IN4 ;
  wire \NlwInverterSignal_portsel<4>_MC.CE/IN5 ;
  wire \NlwInverterSignal_portsel<5>_MC.CE/IN0 ;
  wire \NlwInverterSignal_portsel<5>_MC.CE/IN2 ;
  wire \NlwInverterSignal_portsel<5>_MC.CE/IN4 ;
  wire \NlwInverterSignal_portsel<5>_MC.CE/IN5 ;
  wire \NlwInverterSignal_portsel<6>_MC.CE/IN1 ;
  wire \NlwInverterSignal_portsel<6>_MC.CE/IN4 ;
  wire \NlwInverterSignal_portsel<6>_MC.CE/IN5 ;
  wire \NlwInverterSignal_portsel<7>_MC.CE/IN0 ;
  wire \NlwInverterSignal_portsel<7>_MC.CE/IN1 ;
  wire \NlwInverterSignal_portsel<7>_MC.CE/IN4 ;
  wire \NlwInverterSignal_portsel<7>_MC.CE/IN5 ;
  wire \NlwInverterSignal_scl_n_MC.D1/IN0 ;
  wire \NlwInverterSignal_scl_n_MC.D1/IN1 ;
  wire \NlwInverterSignal_sda_MC.D/IN0 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_0/IN5 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_2/IN5 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_3/IN5 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_4/IN1 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_4/IN2 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_4/IN4 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_4/IN5 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_5/IN0 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_5/IN1 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_5/IN3 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_5/IN5 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_6/IN0 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_6/IN1 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_6/IN3 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_6/IN5 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_7/IN0 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_7/IN2 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_7/IN5 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_8/IN0 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_8/IN1 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_8/IN2 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_8/IN3 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_8/IN5 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_9/IN0 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_9/IN4 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_9/IN5 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_10/IN0 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_10/IN2 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_10/IN4 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_10/IN5 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_11/IN0 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_11/IN1 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_11/IN6 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_12/IN0 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_12/IN1 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_12/IN5 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_13/IN0 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_13/IN3 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_13/IN5 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_14/IN0 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_14/IN3 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_14/IN4 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_14/IN5 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_15/IN0 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_15/IN1 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_15/IN3 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_15/IN4 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_15/IN5 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_16/IN0 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_16/IN1 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_16/IN2 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_16/IN4 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_16/IN5 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_17/IN0 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_17/IN2 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_17/IN3 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_17/IN4 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_17/IN5 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_18/IN0 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_18/IN1 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_18/IN2 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_18/IN3 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_18/IN4 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_18/IN5 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_19/IN0 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_19/IN1 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_19/IN2 ;
  wire \NlwInverterSignal_sda_MC.D2_PT_19/IN5 ;
  wire \NlwInverterSignal_FOOBAR1__ctinst/5/IN0 ;
  wire \NlwInverterSignal_FOOBAR1__ctinst/5/IN1 ;
  wire \NlwInverterSignal_FOOBAR2__ctinst/5/IN0 ;
  wire \NlwInverterSignal_FOOBAR2__ctinst/5/IN1 ;
  wire \NlwInverterSignal_FOOBAR2__ctinst/6/IN0 ;
  wire \NlwInverterSignal_FOOBAR2__ctinst/6/IN1 ;
  wire [9 : 0] inport_pre;
  wire [5 : 0] state;
  initial $sdf_annotate("netgen/fit/i2c_timesim.sdf");
  X_IPAD \clr_n.PAD  (
    .PAD(clr_n)
  );
  X_BUF \clr_n_II/UIM  (
    .I(clr_n),
    .O(\clr_n_II/UIM_3 )
  );
  X_INV \clr_n_II/FSR-  (
    .I(clr_n),
    .O(\clr_n_II/FSR-_4 )
  );
  X_IPAD \inport<10>.PAD  (
    .PAD(inport[10])
  );
  X_BUF \inport<10>_II/UIM  (
    .I(inport[10]),
    .O(\inport<10>_II/UIM_5 )
  );
  X_IPAD \inport<11>.PAD  (
    .PAD(inport[11])
  );
  X_BUF \inport<11>_II/UIM  (
    .I(inport[11]),
    .O(\inport<11>_II/UIM_6 )
  );
  X_IPAD \inport<14>.PAD  (
    .PAD(inport[14])
  );
  X_BUF \inport<14>_II/UIM  (
    .I(inport[14]),
    .O(\inport<14>_II/UIM_7 )
  );
  X_IPAD \inport<15>.PAD  (
    .PAD(inport[15])
  );
  X_BUF \inport<15>_II/UIM  (
    .I(inport[15]),
    .O(\inport<15>_II/UIM_8 )
  );
  X_IPAD \inport<2>.PAD  (
    .PAD(inport[2])
  );
  X_BUF \inport<2>_II/UIM  (
    .I(inport[2]),
    .O(\inport<2>_II/UIM_9 )
  );
  X_IPAD \inport<7>.PAD  (
    .PAD(inport[7])
  );
  X_BUF \inport<7>_II/UIM  (
    .I(inport[7]),
    .O(\inport<7>_II/UIM_10 )
  );
  X_IPAD \inport<8>.PAD  (
    .PAD(inport[8])
  );
  X_BUF \inport<8>_II/UIM  (
    .I(inport[8]),
    .O(\inport<8>_II/UIM_11 )
  );
  X_IPAD \inport<9>.PAD  (
    .PAD(inport[9])
  );
  X_BUF \inport<9>_II/UIM  (
    .I(inport[9]),
    .O(\inport<9>_II/UIM_12 )
  );
  X_IPAD \inport<0>.PAD  (
    .PAD(inport[0])
  );
  X_BUF \inport<0>_II/UIM  (
    .I(inport[0]),
    .O(\inport<0>_II/UIM_13 )
  );
  X_BUF \inport<0>_II/IREG  (
    .I(inport[0]),
    .O(\inport<0>_II/IREG_14 )
  );
  X_OR2 \inport_pre<0>_MC_tsimcreated_prld_  (
    .I0(\clr_n_II/FSR-_4 ),
    .I1(Gnd_15),
    .O(\inport_pre<0>_MC_tsimcreated_prld__16 )
  );
  X_ZERO Gnd (
    .O(Gnd_15)
  );
  defparam \inport_pre<0>_MC.REG .INIT = 1'b0;
  X_FF \inport_pre<0>_MC.REG  (
    .I(\inport<0>_II/IREG_14 ),
    .CE(\inport_pre<0>_MC.CE_18 ),
    .CLK(\scl_II/FCLK_17 ),
    .SET(Gnd_15),
    .RST(\inport_pre<0>_MC_tsimcreated_prld__16 ),
    .O(inport_pre[0])
  );
  X_BUF \sda_II/UIM  (
    .I(sda),
    .O(\sda_II/UIM_19 )
  );
  X_BUF \sda_II/FCLK  (
    .I(sda),
    .O(\sda_II/FCLK_20 )
  );
  X_IPAD \scl.PAD  (
    .PAD(scl)
  );
  X_BUF \scl_II/UIM  (
    .I(scl),
    .O(\scl_II/UIM_21 )
  );
  X_BUF \scl_II/FCLK  (
    .I(scl),
    .O(\scl_II/FCLK_17 )
  );
  X_IPAD \inport<1>.PAD  (
    .PAD(inport[1])
  );
  X_BUF \inport<1>_II/UIM  (
    .I(inport[1]),
    .O(\inport<1>_II/UIM_22 )
  );
  X_BUF \inport<1>_II/IREG  (
    .I(inport[1]),
    .O(\inport<1>_II/IREG_23 )
  );
  X_OR2 \inport_pre<1>_MC_tsimcreated_prld_  (
    .I0(\clr_n_II/FSR-_4 ),
    .I1(Gnd_15),
    .O(\inport_pre<1>_MC_tsimcreated_prld__24 )
  );
  defparam \inport_pre<1>_MC.REG .INIT = 1'b0;
  X_FF \inport_pre<1>_MC.REG  (
    .I(\inport<1>_II/IREG_23 ),
    .CE(\inport_pre<1>_MC.CE_25 ),
    .CLK(\scl_II/FCLK_17 ),
    .SET(Gnd_15),
    .RST(\inport_pre<1>_MC_tsimcreated_prld__24 ),
    .O(inport_pre[1])
  );
  X_IPAD \inport<3>.PAD  (
    .PAD(inport[3])
  );
  X_BUF \inport<3>_II/UIM  (
    .I(inport[3]),
    .O(\inport<3>_II/UIM_26 )
  );
  X_BUF \inport<3>_II/IREG  (
    .I(inport[3]),
    .O(\inport<3>_II/IREG_27 )
  );
  X_OR2 \inport_pre<3>_MC_tsimcreated_prld_  (
    .I0(\clr_n_II/FSR-_4 ),
    .I1(Gnd_15),
    .O(\inport_pre<3>_MC_tsimcreated_prld__28 )
  );
  defparam \inport_pre<3>_MC.REG .INIT = 1'b0;
  X_FF \inport_pre<3>_MC.REG  (
    .I(\inport<3>_II/IREG_27 ),
    .CE(\inport_pre<3>_MC.CE_29 ),
    .CLK(\scl_II/FCLK_17 ),
    .SET(Gnd_15),
    .RST(\inport_pre<3>_MC_tsimcreated_prld__28 ),
    .O(inport_pre[3])
  );
  X_IPAD \inport<4>.PAD  (
    .PAD(inport[4])
  );
  X_BUF \inport<4>_II/UIM  (
    .I(inport[4]),
    .O(\inport<4>_II/UIM_30 )
  );
  X_BUF \inport<4>_II/IREG  (
    .I(inport[4]),
    .O(\inport<4>_II/IREG_31 )
  );
  X_OR2 \inport_pre<4>_MC_tsimcreated_prld_  (
    .I0(\clr_n_II/FSR-_4 ),
    .I1(Gnd_15),
    .O(\inport_pre<4>_MC_tsimcreated_prld__32 )
  );
  defparam \inport_pre<4>_MC.REG .INIT = 1'b0;
  X_FF \inport_pre<4>_MC.REG  (
    .I(\inport<4>_II/IREG_31 ),
    .CE(\inport_pre<4>_MC.CE_33 ),
    .CLK(\scl_II/FCLK_17 ),
    .SET(Gnd_15),
    .RST(\inport_pre<4>_MC_tsimcreated_prld__32 ),
    .O(inport_pre[4])
  );
  X_IPAD \inport<5>.PAD  (
    .PAD(inport[5])
  );
  X_BUF \inport<5>_II/UIM  (
    .I(inport[5]),
    .O(\inport<5>_II/UIM_34 )
  );
  X_BUF \inport<5>_II/IREG  (
    .I(inport[5]),
    .O(\inport<5>_II/IREG_35 )
  );
  X_OR2 \inport_pre<5>_MC_tsimcreated_prld_  (
    .I0(\clr_n_II/FSR-_4 ),
    .I1(Gnd_15),
    .O(\inport_pre<5>_MC_tsimcreated_prld__36 )
  );
  defparam \inport_pre<5>_MC.REG .INIT = 1'b0;
  X_FF \inport_pre<5>_MC.REG  (
    .I(\inport<5>_II/IREG_35 ),
    .CE(\inport_pre<5>_MC.CE_37 ),
    .CLK(\scl_II/FCLK_17 ),
    .SET(Gnd_15),
    .RST(\inport_pre<5>_MC_tsimcreated_prld__36 ),
    .O(inport_pre[5])
  );
  X_IPAD \inport<6>.PAD  (
    .PAD(inport[6])
  );
  X_BUF \inport<6>_II/UIM  (
    .I(inport[6]),
    .O(\inport<6>_II/UIM_38 )
  );
  X_BUF \inport<6>_II/IREG  (
    .I(inport[6]),
    .O(\inport<6>_II/IREG_39 )
  );
  X_OR2 \inport_pre<6>_MC_tsimcreated_prld_  (
    .I0(\clr_n_II/FSR-_4 ),
    .I1(Gnd_15),
    .O(\inport_pre<6>_MC_tsimcreated_prld__40 )
  );
  defparam \inport_pre<6>_MC.REG .INIT = 1'b0;
  X_FF \inport_pre<6>_MC.REG  (
    .I(\inport<6>_II/IREG_39 ),
    .CE(\inport_pre<6>_MC.CE_41 ),
    .CLK(\scl_II/FCLK_17 ),
    .SET(Gnd_15),
    .RST(\inport_pre<6>_MC_tsimcreated_prld__40 ),
    .O(inport_pre[6])
  );
  X_IPAD \inport<12>.PAD  (
    .PAD(inport[12])
  );
  X_BUF \inport<12>_II/UIM  (
    .I(inport[12]),
    .O(\inport<12>_II/UIM_42 )
  );
  X_BUF \inport<12>_II/IREG  (
    .I(inport[12]),
    .O(\inport<12>_II/IREG_43 )
  );
  X_OR2 \inport_pre<7>_MC_tsimcreated_prld_  (
    .I0(\clr_n_II/FSR-_4 ),
    .I1(Gnd_15),
    .O(\inport_pre<7>_MC_tsimcreated_prld__44 )
  );
  defparam \inport_pre<7>_MC.REG .INIT = 1'b0;
  X_FF \inport_pre<7>_MC.REG  (
    .I(\inport<12>_II/IREG_43 ),
    .CE(\inport_pre<7>_MC.CE_45 ),
    .CLK(\scl_II/FCLK_17 ),
    .SET(Gnd_15),
    .RST(\inport_pre<7>_MC_tsimcreated_prld__44 ),
    .O(inport_pre[7])
  );
  X_IPAD \inport<13>.PAD  (
    .PAD(inport[13])
  );
  X_BUF \inport<13>_II/UIM  (
    .I(inport[13]),
    .O(\inport<13>_II/UIM_46 )
  );
  X_BUF \inport<13>_II/IREG  (
    .I(inport[13]),
    .O(\inport<13>_II/IREG_47 )
  );
  X_OR2 \inport_pre<8>_MC_tsimcreated_prld_  (
    .I0(\clr_n_II/FSR-_4 ),
    .I1(Gnd_15),
    .O(\inport_pre<8>_MC_tsimcreated_prld__48 )
  );
  defparam \inport_pre<8>_MC.REG .INIT = 1'b0;
  X_FF \inport_pre<8>_MC.REG  (
    .I(\inport<13>_II/IREG_47 ),
    .CE(\inport_pre<8>_MC.CE_49 ),
    .CLK(\scl_II/FCLK_17 ),
    .SET(Gnd_15),
    .RST(\inport_pre<8>_MC_tsimcreated_prld__48 ),
    .O(inport_pre[8])
  );
  X_IPAD \scl_int.PAD  (
    .PAD(scl_int)
  );
  X_BUF \scl_int_II/FCLK  (
    .I(scl_int),