i2c_timesim.v

在一个32单元CPLD中实现的I2C SLave device

////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.
////////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: J.30
//  \   \         Application: netgen
//  /   /         Filename: i2c_timesim.v
// /___/   /\     Timestamp: Wed Jul 16 11:44:42 2008
// \   \  /  \ 
//  \___\/\___\
//             
// Command	: -intstyle ise -sdf_anno true -sdf_path netgen/fit -insert_glbl true -w -dir netgen/fit -ofmt verilog -sim i2c.nga i2c_timesim.v 
// Device	: XC2C32A-6-VQ44 (Speed File: Version 14.0 Advance Product Specification)
// Input file	: i2c.nga
// Output file	: D:\PY\Widecom\i2c_x\i2c_10a\netgen\fit\i2c_timesim.v
// # of Modules	: 1
// Design Name	: i2c.nga
// Xilinx        : C:\Xilinx91i
//             
// Purpose:    
//     This verilog netlist is a verification model and uses simulation 
//     primitives which may not represent the true implementation of the 
//     device, however the netlist is functionally correct and should not 
//     be modified. This file cannot be synthesized and should only be used 
//     with supported simulation tools.
//             
// Reference:  
//     Development System Reference Guide, Chapter 23
//     Synthesis and Simulation Design Guide, Chapter 6
//             
////////////////////////////////////////////////////////////////////////////////

`timescale 1 ns/1 ps

module i2c (
  clr_n, scl, scl_int, outport, scl_n, sda, inport, portsel
);
  input clr_n;
  input scl;
  input scl_int;
  output outport;
  output scl_n;
  inout sda;
  input [15 : 0] inport;
  output [7 : 0] portsel;
  wire \clr_n_II/UIM_3 ;
  wire \clr_n_II/FSR-_4 ;
  wire \inport<10>_II/UIM_5 ;
  wire \inport<11>_II/UIM_6 ;
  wire \inport<14>_II/UIM_7 ;
  wire \inport<15>_II/UIM_8 ;
  wire \inport<2>_II/UIM_9 ;
  wire \inport<7>_II/UIM_10 ;
  wire \inport<8>_II/UIM_11 ;
  wire \inport<9>_II/UIM_12 ;
  wire \inport<0>_II/UIM_13 ;
  wire \inport<0>_II/IREG_14 ;
  wire Gnd_15;
  wire \inport_pre<0>_MC_tsimcreated_prld__16 ;
  wire \scl_II/FCLK_17 ;
  wire \inport_pre<0>_MC.CE_18 ;
  wire \sda_II/UIM_19 ;
  wire \sda_II/FCLK_20 ;
  wire \scl_II/UIM_21 ;
  wire \inport<1>_II/UIM_22 ;
  wire \inport<1>_II/IREG_23 ;
  wire \inport_pre<1>_MC_tsimcreated_prld__24 ;
  wire \inport_pre<1>_MC.CE_25 ;
  wire \inport<3>_II/UIM_26 ;
  wire \inport<3>_II/IREG_27 ;
  wire \inport_pre<3>_MC_tsimcreated_prld__28 ;
  wire \inport_pre<3>_MC.CE_29 ;
  wire \inport<4>_II/UIM_30 ;
  wire \inport<4>_II/IREG_31 ;
  wire \inport_pre<4>_MC_tsimcreated_prld__32 ;
  wire \inport_pre<4>_MC.CE_33 ;
  wire \inport<5>_II/UIM_34 ;
  wire \inport<5>_II/IREG_35 ;
  wire \inport_pre<5>_MC_tsimcreated_prld__36 ;
  wire \inport_pre<5>_MC.CE_37 ;
  wire \inport<6>_II/UIM_38 ;
  wire \inport<6>_II/IREG_39 ;
  wire \inport_pre<6>_MC_tsimcreated_prld__40 ;
  wire \inport_pre<6>_MC.CE_41 ;
  wire \inport<12>_II/UIM_42 ;
  wire \inport<12>_II/IREG_43 ;
  wire \inport_pre<7>_MC_tsimcreated_prld__44 ;
  wire \inport_pre<7>_MC.CE_45 ;
  wire \inport<13>_II/UIM_46 ;
  wire \inport<13>_II/IREG_47 ;
  wire \inport_pre<8>_MC_tsimcreated_prld__48 ;
  wire \inport_pre<8>_MC.CE_49 ;
  wire \scl_int_II/FCLK_50 ;
  wire \outport_MC.Q_51 ;
  wire \portsel<0>_MC.Q_52 ;
  wire \portsel<1>_MC.Q_53 ;
  wire \portsel<2>_MC.Q_54 ;
  wire \portsel<3>_MC.Q_55 ;
  wire \portsel<4>_MC.Q_56 ;
  wire \portsel<5>_MC.Q_57 ;
  wire \portsel<6>_MC.Q_58 ;
  wire \portsel<7>_MC.Q_59 ;
  wire \scl_n_MC.Q_60 ;
  wire \sda_MC.Q_61 ;
  wire \outport_MC.Q_tsimrenamed_net__62 ;
  wire \outport_MC.D_63 ;
  wire \outport_MC.D1_64 ;
  wire \outport_MC.D2_65 ;
  wire N_PZ_186_66;
  wire \outport_MC.D2_PT_0_67 ;
  wire \outport_MC.D2_PT_1_68 ;
  wire \outport_MC.D2_PT_2_69 ;
  wire \outport_MC.D2_PT_3_70 ;
  wire \outport_MC.D2_PT_4_71 ;
  wire \outport_MC.D2_PT_5_72 ;
  wire \outport_MC.D2_PT_6_73 ;
  wire \outport_MC.D2_PT_7_74 ;
  wire \outport_MC.D2_PT_8_75 ;
  wire \outport_MC.D2_PT_9_76 ;
  wire \outport_MC.D2_PT_10_77 ;
  wire \outport_MC.D2_PT_11_78 ;
  wire \outport_MC.D2_PT_12_79 ;
  wire \outport_MC.D2_PT_13_80 ;
  wire \outport_MC.D2_PT_14_81 ;
  wire \outport_MC.D2_PT_15_82 ;
  wire \outport_MC.D2_PT_16_83 ;
  wire \outport_MC.D2_PT_17_84 ;
  wire \outport_MC.D2_PT_18_85 ;
  wire \outport_MC.D2_PT_19_86 ;
  wire \state<0>_MC.Q ;
  wire \state<0>_MC.D_87 ;
  wire \state<0>_MC_tsimcreated_xor__88 ;
  wire \FOOBAR1__ctinst/6_89 ;
  wire \state<0>_MC_tsimcreated_set_and_noreset__90 ;
  wire \state<0>_MC_tsimcreated_prld__91 ;
  wire Vcc_92;
  wire \state<0>_MC.D1_93 ;
  wire \state<0>_MC.D2_94 ;
  wire \state<0>_MC.D2_PT_0_95 ;
  wire \state<0>_MC.D2_PT_1_96 ;
  wire \state<0>_MC.D2_PT_2_97 ;
  wire \state<0>_MC.D2_PT_3_98 ;
  wire \state<0>_MC.D2_PT_4_99 ;
  wire \state<2>_MC.Q ;
  wire \state<2>_MC.D_100 ;
  wire \state<2>_MC_tsimcreated_xor__101 ;
  wire \FOOBAR1__ctinst/5_102 ;
  wire \state<2>_MC_tsimcreated_prld__103 ;
  wire \state<2>_MC.D1_104 ;
  wire \state<2>_MC.D2_105 ;
  wire \state<2>_MC.D2_PT_0_106 ;
  wire \state<2>_MC.D2_PT_1_107 ;
  wire \state<2>_MC.D2_PT_2_108 ;
  wire \state<2>_MC.D2_PT_3_109 ;
  wire \state<2>_MC.D2_PT_4_110 ;
  wire \state<1>_MC.Q ;
  wire \state<1>_MC_tsimcreated_prld__111 ;
  wire \state<1>_MC.D_112 ;
  wire \state<1>_MC.D1_113 ;
  wire \state<1>_MC.D2_114 ;
  wire \state<1>_MC.D2_PT_0_115 ;
  wire \state<1>_MC.D2_PT_1_116 ;
  wire \state<1>_MC.D2_PT_2_117 ;
  wire \state<1>_MC.D2_PT_3_118 ;
  wire \state<3>_MC.Q ;
  wire \state<3>_MC.D_119 ;
  wire \state<3>_MC_tsimcreated_xor__120 ;
  wire \state<3>_MC_tsimcreated_prld__121 ;
  wire \state<3>_MC.D1_122 ;
  wire \state<3>_MC.D2_123 ;
  wire \state<3>_MC.D2_PT_0_124 ;
  wire \state<3>_MC.D2_PT_1_125 ;
  wire \state<3>_MC.D2_PT_2_126 ;
  wire \state<3>_MC.D2_PT_3_127 ;
  wire \state<4>_MC.Q ;
  wire \state<4>_MC.D_128 ;
  wire \state<4>_MC_tsimcreated_xor__129 ;
  wire \state<4>_MC_tsimcreated_prld__130 ;
  wire \state<4>_MC.D1_131 ;
  wire \state<4>_MC.D2_132 ;
  wire \state<4>_MC.D2_PT_0_133 ;
  wire \state<4>_MC.D2_PT_1_134 ;
  wire \state<4>_MC.D2_PT_2_135 ;
  wire \state<4>_MC.D2_PT_3_136 ;
  wire \state<4>_MC.D2_PT_4_137 ;
  wire \state<5>_MC.Q ;
  wire \state<5>_MC.D_138 ;
  wire \state<5>_MC_tsimcreated_xor__139 ;
  wire \state<5>_MC_tsimcreated_prld__140 ;
  wire \state<5>_MC.D1_141 ;
  wire \state<5>_MC.D2_142 ;
  wire \state<5>_MC.D2_PT_0_143 ;
  wire \state<5>_MC.D2_PT_1_144 ;
  wire \N_PZ_227_MC.Q_145 ;
  wire N_PZ_227_146;
  wire \N_PZ_227_MC.D_147 ;
  wire \N_PZ_227_MC.D1_148 ;
  wire \N_PZ_227_MC.D2_149 ;
  wire start_150;
  wire \start_MC.Q ;
  wire \FOOBAR2__ctinst/5_151 ;
  wire start_MC_tsimcreated_prld__152;
  wire \start_MC.D_153 ;
  wire \start_MC.REG_tsimcreated_inv_sda_II/FCLK_154 ;
  wire \start_MC.D1_155 ;
  wire \start_MC.D2_156 ;
  wire \N_PZ_222_MC.Q_157 ;
  wire N_PZ_222_158;
  wire \N_PZ_222_MC.D_159 ;
  wire \N_PZ_222_MC.D1_160 ;
  wire \N_PZ_222_MC.D2_161 ;
  wire \inport_pre<9>_MC.Q ;
  wire \inport_pre<9>_MC.D_162 ;
  wire \inport_pre<9>_MC_tsimcreated_xor__163 ;
  wire \inport_pre<9>_MC_tsimcreated_prld__164 ;
  wire \inport_pre<9>_MC.D1_165 ;
  wire \inport_pre<9>_MC.D2_166 ;
  wire \inport_pre<9>_MC.D2_PT_0_167 ;
  wire \inport_pre<9>_MC.D2_PT_1_168 ;
  wire \inport_pre<9>_MC.D2_PT_2_169 ;
  wire \N_PZ_186_MC.Q_170 ;
  wire \N_PZ_186_MC.D_171 ;
  wire \N_PZ_186_MC.D1_172 ;
  wire \N_PZ_186_MC.D2_173 ;
  wire \inport_pre<2>_MC.Q ;
  wire \inport_pre<2>_MC.D_174 ;
  wire \inport_pre<2>_MC_tsimcreated_xor__175 ;
  wire \inport_pre<2>_MC_tsimcreated_prld__176 ;
  wire \inport_pre<2>_MC.D1_177 ;
  wire \inport_pre<2>_MC.D2_178 ;
  wire \portsel<0>_MC.Q_tsimrenamed_net_ ;
  wire \portsel<0>_MC_tsimcreated_prld__179 ;
  wire \portsel<0>_MC.D_180 ;
  wire \portsel<0>_MC.CE_181 ;
  wire \portsel<0>_MC.D1_182 ;
  wire \portsel<0>_MC.D2_183 ;
  wire \portsel<1>_MC.Q_tsimrenamed_net_ ;
  wire \portsel<1>_MC_tsimcreated_prld__184 ;
  wire \portsel<1>_MC.D_185 ;
  wire \portsel<1>_MC.CE_186 ;
  wire \portsel<1>_MC.D1_187 ;
  wire \portsel<1>_MC.D2_188 ;
  wire \portsel<2>_MC.Q_tsimrenamed_net_ ;
  wire \portsel<2>_MC_tsimcreated_prld__189 ;
  wire \portsel<2>_MC.D_190 ;
  wire \portsel<2>_MC.CE_191 ;
  wire \portsel<2>_MC.D1_192 ;
  wire \portsel<2>_MC.D2_193 ;
  wire \portsel<3>_MC.Q_tsimrenamed_net_ ;
  wire \portsel<3>_MC_tsimcreated_prld__194 ;
  wire \portsel<3>_MC.D_195 ;
  wire \portsel<3>_MC.CE_196 ;
  wire \portsel<3>_MC.D1_197 ;
  wire \portsel<3>_MC.D2_198 ;
  wire \portsel<4>_MC.Q_tsimrenamed_net_ ;
  wire \portsel<4>_MC_tsimcreated_prld__199 ;
  wire \portsel<4>_MC.D_200 ;
  wire \portsel<4>_MC.CE_201 ;
  wire \portsel<4>_MC.D1_202 ;
  wire \portsel<4>_MC.D2_203 ;
  wire \portsel<5>_MC.Q_tsimrenamed_net_ ;
  wire \portsel<5>_MC_tsimcreated_prld__204 ;
  wire \portsel<5>_MC.D_205 ;
  wire \portsel<5>_MC.CE_206 ;
  wire \portsel<5>_MC.D1_207 ;
  wire \portsel<5>_MC.D2_208 ;
  wire \portsel<6>_MC.Q_tsimrenamed_net_ ;
  wire \portsel<6>_MC_tsimcreated_prld__209 ;
  wire \portsel<6>_MC.D_210 ;
  wire \portsel<6>_MC.CE_211 ;
  wire \portsel<6>_MC.D1_212 ;
  wire \portsel<6>_MC.D2_213 ;
  wire \portsel<7>_MC.Q_tsimrenamed_net_ ;
  wire \portsel<7>_MC_tsimcreated_prld__214 ;
  wire \portsel<7>_MC.D_215 ;
  wire \portsel<7>_MC.CE_216 ;
  wire \portsel<7>_MC.D1_217 ;
  wire \portsel<7>_MC.D2_218 ;
  wire \scl_n_MC.Q_tsimrenamed_net__219 ;
  wire \scl_n_MC.D_220 ;
  wire \scl_n_MC.D1_221 ;
  wire \scl_n_MC.D2_222 ;
  wire \sda_MC.Q_tsimrenamed_net_ ;
  wire \FOOBAR2__ctinst/6_223 ;
  wire sda_MC_tsimcreated_prld__224;
  wire \sda_MC.D_225 ;
  wire \sda_MC.D1_226 ;
  wire \sda_MC.D2_227 ;
  wire \sda_MC.D2_PT_0_228 ;
  wire \sda_MC.D2_PT_1_229 ;
  wire \sda_MC.D2_PT_2_230 ;
  wire \sda_MC.D2_PT_3_231 ;
  wire \sda_MC.D2_PT_4_232 ;
  wire \sda_MC.D2_PT_5_233 ;
  wire \sda_MC.D2_PT_6_234 ;
  wire \sda_MC.D2_PT_7_235 ;
  wire \sda_MC.D2_PT_8_236 ;
  wire \sda_MC.D2_PT_9_237 ;
  wire \sda_MC.D2_PT_10_238 ;
  wire \sda_MC.D2_PT_11_239 ;
  wire \sda_MC.D2_PT_12_240 ;
  wire \sda_MC.D2_PT_13_241 ;
  wire \sda_MC.D2_PT_14_242 ;
  wire \sda_MC.D2_PT_15_243 ;
  wire \sda_MC.D2_PT_16_244 ;
  wire \sda_MC.D2_PT_17_245 ;
  wire \sda_MC.D2_PT_18_246 ;
  wire \sda_MC.D2_PT_19_247 ;
  wire \NlwInverterSignal_outport/CTL ;
  wire \NlwInverterSignal_scl_n/CTL ;
  wire \NlwInverterSignal_sda/CTL ;
  wire \NlwInverterSignal_outport_MC.D/IN0 ;
  wire \NlwInverterSignal_outport_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_outport_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_outport_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_outport_MC.D2_PT_4/IN0 ;
  wire \NlwInverterSignal_outport_MC.D2_PT_5/IN1 ;
  wire \NlwInverterSignal_outport_MC.D2_PT_6/IN0 ;
  wire \NlwInverterSignal_outport_MC.D2_PT_7/IN1 ;
  wire \NlwInverterSignal_outport_MC.D2_PT_8/IN0 ;
  wire \NlwInverterSignal_outport_MC.D2_PT_9/IN1 ;
  wire \NlwInverterSignal_outport_MC.D2_PT_10/IN0 ;
  wire \NlwInverterSignal_outport_MC.D2_PT_11/IN1 ;
  wire \NlwInverterSignal_outport_MC.D2_PT_12/IN0 ;
  wire \NlwInverterSignal_outport_MC.D2_PT_13/IN1 ;
  wire \NlwInverterSignal_outport_MC.D2_PT_14/IN0 ;
  wire \NlwInverterSignal_outport_MC.D2_PT_15/IN1 ;
  wire \NlwInverterSignal_outport_MC.D2_PT_16/IN0 ;
  wire \NlwInverterSignal_outport_MC.D2_PT_17/IN1 ;
  wire \NlwInverterSignal_outport_MC.D2_PT_18/IN0 ;
  wire \NlwInverterSignal_outport_MC.D2_PT_19/IN0 ;
  wire \NlwInverterSignal_outport_MC.D2_PT_19/IN1 ;
  wire \NlwInverterSignal_inport_pre<0>_MC.CE/IN2 ;
  wire \NlwInverterSignal_inport_pre<0>_MC.CE/IN5 ;
  wire \NlwInverterSignal_state<0>_MC_tsimcreated_set_and_noreset_/IN0 ;
  wire \NlwInverterSignal_state<0>_MC.D/IN0 ;
  wire \NlwInverterSignal_state<0>_MC.D2_PT_0/IN0 ;
  wire \NlwInverterSignal_state<0>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_state<0>_MC.D2_PT_0/IN2 ;
  wire \NlwInverterSignal_state<0>_MC.D2_PT_0/IN3 ;
  wire \NlwInverterSignal_state<0>_MC.D2_PT_0/IN4 ;
  wire \NlwInverterSignal_state<0>_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_state<0>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_state<0>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_state<0>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_state<0>_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_state<0>_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_state<0>_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_state<0>_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_state<0>_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_state<0>_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_state<0>_MC.D2_PT_2/IN5 ;
  wire \NlwInverterSignal_state<0>_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_state<0>_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_state<0>_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_state<0>_MC.D2_PT_3/IN3 ;
  wire \NlwInverterSignal_state<0>_MC.D2_PT_3/IN4 ;
  wire \NlwInverterSignal_state<0>_MC.D2_PT_4/IN0 ;
  wire \NlwInverterSignal_state<0>_MC.D2_PT_4/IN2 ;
  wire \NlwInverterSignal_state<0>_MC.D2_PT_4/IN5 ;
  wire \NlwInverterSignal_state<0>_MC.D2_PT_4/IN6 ;
  wire \NlwInverterSignal_state<2>_MC.D2_PT_0/IN1 ;
  wire \NlwInverterSignal_state<2>_MC.D2_PT_0/IN5 ;
  wire \NlwInverterSignal_state<2>_MC.D2_PT_1/IN2 ;
  wire \NlwInverterSignal_state<2>_MC.D2_PT_1/IN3 ;
  wire \NlwInverterSignal_state<2>_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_state<2>_MC.D2_PT_1/IN5 ;
  wire \NlwInverterSignal_state<2>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_state<2>_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_state<2>_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_state<2>_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_state<2>_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_state<2>_MC.D2_PT_3/IN3 ;
  wire \NlwInverterSignal_state<2>_MC.D2_PT_3/IN4 ;
  wire \NlwInverterSignal_state<2>_MC.D2_PT_3/IN5 ;
  wire \NlwInverterSignal_state<2>_MC.D2_PT_4/IN0 ;
  wire \NlwInverterSignal_state<2>_MC.D2_PT_4/IN2 ;
  wire \NlwInverterSignal_state<2>_MC.D2_PT_4/IN5 ;
  wire \NlwInverterSignal_state<2>_MC.D2_PT_4/IN6 ;
  wire \NlwInverterSignal_state<1>_MC.D/IN0 ;
  wire \NlwInverterSignal_state<1>_MC.D2_PT_1/IN0 ;
  wire \NlwInverterSignal_state<1>_MC.D2_PT_1/IN1 ;
  wire \NlwInverterSignal_state<1>_MC.D2_PT_2/IN1 ;
  wire \NlwInverterSignal_state<1>_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_state<1>_MC.D2_PT_2/IN3 ;
  wire \NlwInverterSignal_state<1>_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_state<1>_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_state<1>_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_state<1>_MC.D2_PT_3/IN3 ;
  wire \NlwInverterSignal_state<1>_MC.D2_PT_3/IN4 ;
  wire \NlwInverterSignal_state<3>_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_state<3>_MC.D2_PT_2/IN0 ;
  wire \NlwInverterSignal_state<3>_MC.D2_PT_2/IN2 ;
  wire \NlwInverterSignal_state<3>_MC.D2_PT_2/IN5 ;
  wire \NlwInverterSignal_state<3>_MC.D2_PT_2/IN6 ;
  wire \NlwInverterSignal_state<3>_MC.D2_PT_3/IN0 ;
  wire \NlwInverterSignal_state<3>_MC.D2_PT_3/IN1 ;
  wire \NlwInverterSignal_state<3>_MC.D2_PT_3/IN2 ;
  wire \NlwInverterSignal_state<3>_MC.D2_PT_3/IN4 ;
  wire \NlwInverterSignal_state<3>_MC.D2_PT_3/IN5 ;
  wire \NlwInverterSignal_state<4>_MC.D2_PT_1/IN4 ;
  wire \NlwInverterSignal_state<4>_MC.D2_PT_2/IN4 ;
  wire \NlwInverterSignal_state<4>_MC.D2_PT_3/IN3 ;
  wire \NlwInverterSignal_state<4>_MC.D2_PT_3/IN4 ;
  wire \NlwInverterSignal_state<4>_MC.D2_PT_3/IN5 ;
  wire \NlwInverterSignal_state<4>_MC.D2_PT_4/IN0 ;
  wire \NlwInverterSignal_state<4>_MC.D2_PT_4/IN2 ;
  wire \NlwInverterSignal_state<4>_MC.D2_PT_4/IN5 ;
  wire \NlwInverterSignal_state<4>_MC.D2_PT_4/IN6 ;
  wire \NlwInverterSignal_N_PZ_227_MC.D1/IN1 ;
  wire \NlwInverterSignal_start_MC.D/IN0 ;
  wire \NlwInverterSignal_inport_pre<1>_MC.CE/IN2 ;
  wire \NlwInverterSignal_inport_pre<1>_MC.CE/IN5 ;
  wire \NlwInverterSignal_inport_pre<3>_MC.CE/IN2 ;
  wire \NlwInverterSignal_inport_pre<3>_MC.CE/IN5 ;
  wire \NlwInverterSignal_inport_pre<4>_MC.CE/IN2 ;
  wire \NlwInverterSignal_inport_pre<4>_MC.CE/IN5 ;
  wire \NlwInverterSignal_inport_pre<5>_MC.CE/IN2 ;
  wire \NlwInverterSignal_inport_pre<5>_MC.CE/IN5 ;
  wire \NlwInverterSignal_inport_pre<6>_MC.CE/IN2 ;
  wire \NlwInverterSignal_inport_pre<6>_MC.CE/IN5 ;
  wire \NlwInverterSignal_inport_pre<7>_MC.CE/IN2 ;
  wire \NlwInverterSignal_inport_pre<7>_MC.CE/IN5 ;
  wire \NlwInverterSignal_inport_pre<8>_MC.CE/IN2 ;
  wire \NlwInverterSignal_inport_pre<8>_MC.CE/IN5 ;
  wire \NlwInverterSignal_inport_pre<9>_MC.D2_PT_0/IN1 ;