i2c_timesim.sdf

在一个32单元CPLD中实现的I2C SLave device

          (PORT I1 ( 3000 )( 3000 ))
          (PORT I2 ( 3000 )( 3000 ))
          (PORT I3 ( 3000 )( 3000 ))
          (PORT I4 ( 3000 )( 3000 ))
          (PORT I5 ( 3000 )( 3000 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
          (IOPATH I2 O ( 0 )( 0 ))
          (IOPATH I3 O ( 0 )( 0 ))
          (IOPATH I4 O ( 0 )( 0 ))
          (IOPATH I5 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND6")
    (INSTANCE inport_pre\<8\>_MC\.CE)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 3000 )( 3000 ))
          (PORT I1 ( 3000 )( 3000 ))
          (PORT I2 ( 3000 )( 3000 ))
          (PORT I3 ( 3000 )( 3000 ))
          (PORT I4 ( 3000 )( 3000 ))
          (PORT I5 ( 3000 )( 3000 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
          (IOPATH I2 O ( 0 )( 0 ))
          (IOPATH I3 O ( 0 )( 0 ))
          (IOPATH I4 O ( 0 )( 0 ))
          (IOPATH I5 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_BUF")
    (INSTANCE inport_pre\<9\>)
      (DELAY
        (ABSOLUTE
          (IOPATH I O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_XOR2")
    (INSTANCE inport_pre\<9\>_MC_tsimcreated_xor_)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 0 )( 0 ))
          (PORT I1 ( 200 )( 200 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_OR2")
    (INSTANCE inport_pre\<9\>_MC_tsimcreated_prld_)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 0 )( 0 ))
          (PORT I1 ( 0 )( 0 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_FF")
    (INSTANCE inport_pre\<9\>_MC\.REG)
      (DELAY
        (ABSOLUTE
          (IOPATH CLK O ( 700 )( 700 ))
          (IOPATH SET O ( 1500 )( 1500 ))
          (IOPATH RST O ( 1500 )( 1500 ))
        )
      )
      (TIMINGCHECK
        (SETUPHOLD (posedge I) (posedge CLK) (1800)(200))
        (SETUPHOLD (negedge I) (posedge CLK) (1800)(200))
        (SETUPHOLD (posedge CE) (posedge CLK) (0)(0))
        (PERIOD (posedge CLK) (4400))
        (WIDTH (posedge SET) (6000))
        (WIDTH (posedge RST) (6000))
      )
  )
  (CELL (CELLTYPE "X_XOR2")
    (INSTANCE inport_pre\<9\>_MC\.D)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 0 )( 0 ))
          (PORT I1 ( 0 )( 0 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND8")
    (INSTANCE inport_pre\<9\>_MC\.D2_PT_0)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 1600 )( 1600 ))
          (PORT I1 ( 3000 )( 3000 ))
          (PORT I2 ( 3000 )( 3000 ))
          (PORT I3 ( 3000 )( 3000 ))
          (PORT I4 ( 3000 )( 3000 ))
          (PORT I5 ( 3000 )( 3000 ))
          (PORT I6 ( 3000 )( 3000 ))
          (PORT I7 ( 3000 )( 3000 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
          (IOPATH I2 O ( 0 )( 0 ))
          (IOPATH I3 O ( 0 )( 0 ))
          (IOPATH I4 O ( 0 )( 0 ))
          (IOPATH I5 O ( 0 )( 0 ))
          (IOPATH I6 O ( 0 )( 0 ))
          (IOPATH I7 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND8")
    (INSTANCE inport_pre\<9\>_MC\.D2_PT_1)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 1600 )( 1600 ))
          (PORT I1 ( 3000 )( 3000 ))
          (PORT I2 ( 3000 )( 3000 ))
          (PORT I3 ( 3000 )( 3000 ))
          (PORT I4 ( 3000 )( 3000 ))
          (PORT I5 ( 3000 )( 3000 ))
          (PORT I6 ( 3000 )( 3000 ))
          (PORT I7 ( 3000 )( 3000 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
          (IOPATH I2 O ( 0 )( 0 ))
          (IOPATH I3 O ( 0 )( 0 ))
          (IOPATH I4 O ( 0 )( 0 ))
          (IOPATH I5 O ( 0 )( 0 ))
          (IOPATH I6 O ( 0 )( 0 ))
          (IOPATH I7 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND16")
    (INSTANCE inport_pre\<9\>_MC\.D2_PT_2)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 1600 )( 1600 ))
          (PORT I1 ( 1600 )( 1600 ))
          (PORT I2 ( 3000 )( 3000 ))
          (PORT I3 ( 3000 )( 3000 ))
          (PORT I4 ( 3000 )( 3000 ))
          (PORT I5 ( 3000 )( 3000 ))
          (PORT I6 ( 3000 )( 3000 ))
          (PORT I7 ( 3000 )( 3000 ))
          (PORT I8 ( 3000 )( 3000 ))
          (PORT I9 ( 0 )( 0 ))
          (PORT I10 ( 0 )( 0 ))
          (PORT I11 ( 0 )( 0 ))
          (PORT I12 ( 0 )( 0 ))
          (PORT I13 ( 0 )( 0 ))
          (PORT I14 ( 0 )( 0 ))
          (PORT I15 ( 0 )( 0 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
          (IOPATH I2 O ( 0 )( 0 ))
          (IOPATH I3 O ( 0 )( 0 ))
          (IOPATH I4 O ( 0 )( 0 ))
          (IOPATH I5 O ( 0 )( 0 ))
          (IOPATH I6 O ( 0 )( 0 ))
          (IOPATH I7 O ( 0 )( 0 ))
          (IOPATH I8 O ( 0 )( 0 ))
          (IOPATH I9 O ( 0 )( 0 ))
          (IOPATH I10 O ( 0 )( 0 ))
          (IOPATH I11 O ( 0 )( 0 ))
          (IOPATH I12 O ( 0 )( 0 ))
          (IOPATH I13 O ( 0 )( 0 ))
          (IOPATH I14 O ( 0 )( 0 ))
          (IOPATH I15 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_OR3")
    (INSTANCE inport_pre\<9\>_MC\.D2)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 0 )( 0 ))
          (PORT I1 ( 0 )( 0 ))
          (PORT I2 ( 0 )( 0 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
          (IOPATH I2 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_BUF")
    (INSTANCE N_PZ_186)
      (DELAY
        (ABSOLUTE
          (IOPATH I O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_BUF")
    (INSTANCE N_PZ_186_MC\.Q)
      (DELAY
        (ABSOLUTE
          (IOPATH I O ( 700 )( 700 ))
        )
      )
  )
  (CELL (CELLTYPE "X_XOR2")
    (INSTANCE N_PZ_186_MC\.D)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 0 )( 0 ))
          (PORT I1 ( 0 )( 0 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND2")
    (INSTANCE N_PZ_186_MC\.D1)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 2500 )( 2500 ))
          (PORT I1 ( 2500 )( 2500 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND6")
    (INSTANCE N_PZ_186_MC\.D2)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 1600 )( 1600 ))
          (PORT I1 ( 1600 )( 1600 ))
          (PORT I2 ( 1600 )( 1600 ))
          (PORT I3 ( 1600 )( 1600 ))
          (PORT I4 ( 1600 )( 1600 ))
          (PORT I5 ( 1600 )( 1600 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
          (IOPATH I2 O ( 0 )( 0 ))
          (IOPATH I3 O ( 0 )( 0 ))
          (IOPATH I4 O ( 0 )( 0 ))
          (IOPATH I5 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_BUF")
    (INSTANCE inport_pre\<2\>)
      (DELAY
        (ABSOLUTE
          (IOPATH I O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_XOR2")
    (INSTANCE inport_pre\<2\>_MC_tsimcreated_xor_)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 0 )( 0 ))
          (PORT I1 ( 200 )( 200 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_OR2")
    (INSTANCE inport_pre\<2\>_MC_tsimcreated_prld_)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 0 )( 0 ))
          (PORT I1 ( 0 )( 0 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_FF")
    (INSTANCE inport_pre\<2\>_MC\.REG)
      (DELAY
        (ABSOLUTE
          (IOPATH CLK O ( 700 )( 700 ))
          (IOPATH SET O ( 1500 )( 1500 ))
          (IOPATH RST O ( 1500 )( 1500 ))
        )
      )
      (TIMINGCHECK
        (SETUPHOLD (posedge I) (posedge CLK) (1800)(200))
        (SETUPHOLD (negedge I) (posedge CLK) (1800)(200))
        (SETUPHOLD (posedge CE) (posedge CLK) (0)(0))
        (PERIOD (posedge CLK) (4400))
        (WIDTH (posedge SET) (6000))
        (WIDTH (posedge RST) (6000))
      )
  )
  (CELL (CELLTYPE "X_XOR2")
    (INSTANCE inport_pre\<2\>_MC\.D)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 0 )( 0 ))
          (PORT I1 ( 0 )( 0 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND7")
    (INSTANCE inport_pre\<2\>_MC\.D1)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 2500 )( 2500 ))
          (PORT I1 ( 2500 )( 2500 ))
          (PORT I2 ( 2500 )( 2500 ))
          (PORT I3 ( 2500 )( 2500 ))
          (PORT I4 ( 2500 )( 2500 ))
          (PORT I5 ( 2500 )( 2500 ))
          (PORT I6 ( 2500 )( 2500 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
          (IOPATH I2 O ( 0 )( 0 ))
          (IOPATH I3 O ( 0 )( 0 ))
          (IOPATH I4 O ( 0 )( 0 ))
          (IOPATH I5 O ( 0 )( 0 ))
          (IOPATH I6 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_BUF")
    (INSTANCE portsel\<0\>_MC\.Q)
      (DELAY
        (ABSOLUTE
          (IOPATH I O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_OR2")
    (INSTANCE portsel\<0\>_MC_tsimcreated_prld_)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 0 )( 0 ))
          (PORT I1 ( 0 )( 0 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_FF")
    (INSTANCE portsel\<0\>_MC\.REG)
      (DELAY
        (ABSOLUTE
          (IOPATH CLK O ( 700 )( 700 ))
          (IOPATH SET O ( 1500 )( 1500 ))
          (IOPATH RST O ( 1500 )( 1500 ))
        )
      )
      (TIMINGCHECK
        (SETUPHOLD (posedge I) (posedge CLK) (1800)(200))
        (SETUPHOLD (negedge I) (posedge CLK) (1800)(200))
        (SETUPHOLD (posedge CE) (posedge CLK) (1800)(200))
        (PERIOD (posedge CLK) (4400))
        (WIDTH (posedge SET) (6000))
        (WIDTH (posedge RST) (6000))
      )
  )
  (CELL (CELLTYPE "X_XOR2")
    (INSTANCE portsel\<0\>_MC\.D)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 0 )( 0 ))
          (PORT I1 ( 0 )( 0 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND2")
    (INSTANCE portsel\<0\>_MC\.D2)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 1600 )( 1600 ))
          (PORT I1 ( 1600 )( 1600 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND6")
    (INSTANCE portsel\<0\>_MC\.CE)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 3000 )( 3000 ))
          (PORT I1 ( 3000 )( 3000 ))
          (PORT I2 ( 3000 )( 3000 ))
          (PORT I3 ( 3000 )( 3000 ))
          (PORT I4 ( 3000 )( 3000 ))
          (PORT I5 ( 3000 )( 3000 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
          (IOPATH I2 O ( 0 )( 0 ))
          (IOPATH I3 O ( 0 )( 0 ))
          (IOPATH I4 O ( 0 )( 0 ))
          (IOPATH I5 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_BUF")
    (INSTANCE portsel\<1\>_MC\.Q)
      (DELAY
        (ABSOLUTE
          (IOPATH I O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_OR2")
    (INSTANCE portsel\<1\>_MC_tsimcreated_prld_)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 0 )( 0 ))
          (PORT I1 ( 0 )( 0 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_FF")
    (INSTANCE portsel\<1\>_MC\.REG)
      (DELAY
        (ABSOLUTE
          (IOPATH CLK O ( 700 )( 700 ))
          (IOPATH SET O ( 1500 )( 1500 ))
          (IOPATH RST O ( 1500 )( 1500 ))
        )
      )
      (TIMINGCHECK
        (SETUPHOLD (posedge I) (posedge CLK) (1800)(200))
        (SETUPHOLD (negedge I) (posedge CLK) (1800)(200))
        (SETUPHOLD (posedge CE) (posedge CLK) (1800)(200))
        (PERIOD (posedge CLK) (4400))
        (WIDTH (posedge SET) (6000))
        (WIDTH (posedge RST) (6000))
      )
  )
  (CELL (CELLTYPE "X_XOR2")
    (INSTANCE portsel\<1\>_MC\.D)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 0 )( 0 ))
          (PORT I1 ( 0 )( 0 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND2")
    (INSTANCE portsel\<1\>_MC\.D2)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 1600 )( 1600 ))
          (PORT I1 ( 1600 )( 1600 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND6")
    (INSTANCE portsel\<1\>_MC\.CE)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 3000 )( 3000 ))
          (PORT I1 ( 3000 )( 3000 ))
          (PORT I2 ( 3000 )( 3000 ))
          (PORT I3 ( 3000 )( 3000 ))
          (PORT I4 ( 3000 )( 3000 ))
          (PORT I5 ( 3000 )( 3000 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
          (IOPATH I2 O ( 0 )( 0 ))
          (IOPATH I3 O ( 0 )( 0 ))
          (IOPATH I4 O ( 0 )( 0 ))
          (IOPATH I5 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_BUF")
    (INSTANCE portsel\<2\>_MC\.Q)
      (DELAY
        (ABSOLUTE
          (IOPATH I O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_OR2")
    (INSTANCE portsel\<2\>_MC_tsimcreated_prld_)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 0 )( 0 ))
          (PORT I1 ( 0 )( 0 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_FF")
    (INSTANCE portsel\<2\>_MC\.REG)
      (DELAY
        (ABSOLUTE
          (IOPATH CLK O ( 700 )( 700 ))
          (IOPATH SET O ( 1500 )( 1500 ))
          (IOPATH RST O ( 1500 )( 1500 ))
        )
      )
      (TIMINGCHECK
        (SETUPHOLD (posedge I) (posedge CLK) (1800)(20