i2c_timesim.sdf

在一个32单元CPLD中实现的I2C SLave device

        (ABSOLUTE
          (PORT I0 ( 0 )( 0 ))
          (PORT I1 ( 0 )( 0 ))
          (PORT I2 ( 0 )( 0 ))
          (PORT I3 ( 0 )( 0 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
          (IOPATH I2 O ( 0 )( 0 ))
          (IOPATH I3 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_BUF")
    (INSTANCE state\<4\>)
      (DELAY
        (ABSOLUTE
          (IOPATH I O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_XOR2")
    (INSTANCE state\<4\>_MC_tsimcreated_xor_)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 0 )( 0 ))
          (PORT I1 ( 200 )( 200 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_OR2")
    (INSTANCE state\<4\>_MC_tsimcreated_prld_)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 0 )( 0 ))
          (PORT I1 ( 0 )( 0 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_FF")
    (INSTANCE state\<4\>_MC\.REG)
      (DELAY
        (ABSOLUTE
          (IOPATH CLK O ( 700 )( 700 ))
          (IOPATH SET O ( 1500 )( 1500 ))
          (IOPATH RST O ( 1500 )( 1500 ))
        )
      )
      (TIMINGCHECK
        (SETUPHOLD (posedge I) (posedge CLK) (1800)(200))
        (SETUPHOLD (negedge I) (posedge CLK) (1800)(200))
        (SETUPHOLD (posedge CE) (posedge CLK) (0)(0))
        (PERIOD (posedge CLK) (4400))
        (WIDTH (posedge SET) (6000))
        (WIDTH (posedge RST) (6000))
      )
  )
  (CELL (CELLTYPE "X_XOR2")
    (INSTANCE state\<4\>_MC\.D)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 0 )( 0 ))
          (PORT I1 ( 0 )( 0 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND5")
    (INSTANCE state\<4\>_MC\.D2_PT_0)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 3000 )( 3000 ))
          (PORT I1 ( 3000 )( 3000 ))
          (PORT I2 ( 3000 )( 3000 ))
          (PORT I3 ( 3000 )( 3000 ))
          (PORT I4 ( 3000 )( 3000 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
          (IOPATH I2 O ( 0 )( 0 ))
          (IOPATH I3 O ( 0 )( 0 ))
          (IOPATH I4 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND5")
    (INSTANCE state\<4\>_MC\.D2_PT_1)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 3000 )( 3000 ))
          (PORT I1 ( 3000 )( 3000 ))
          (PORT I2 ( 3000 )( 3000 ))
          (PORT I3 ( 3000 )( 3000 ))
          (PORT I4 ( 3000 )( 3000 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
          (IOPATH I2 O ( 0 )( 0 ))
          (IOPATH I3 O ( 0 )( 0 ))
          (IOPATH I4 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND5")
    (INSTANCE state\<4\>_MC\.D2_PT_2)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 3000 )( 3000 ))
          (PORT I1 ( 3000 )( 3000 ))
          (PORT I2 ( 3000 )( 3000 ))
          (PORT I3 ( 3000 )( 3000 ))
          (PORT I4 ( 3000 )( 3000 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
          (IOPATH I2 O ( 0 )( 0 ))
          (IOPATH I3 O ( 0 )( 0 ))
          (IOPATH I4 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND6")
    (INSTANCE state\<4\>_MC\.D2_PT_3)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 3000 )( 3000 ))
          (PORT I1 ( 3000 )( 3000 ))
          (PORT I2 ( 3000 )( 3000 ))
          (PORT I3 ( 3000 )( 3000 ))
          (PORT I4 ( 3000 )( 3000 ))
          (PORT I5 ( 1600 )( 1600 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
          (IOPATH I2 O ( 0 )( 0 ))
          (IOPATH I3 O ( 0 )( 0 ))
          (IOPATH I4 O ( 0 )( 0 ))
          (IOPATH I5 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND7")
    (INSTANCE state\<4\>_MC\.D2_PT_4)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 3000 )( 3000 ))
          (PORT I1 ( 3000 )( 3000 ))
          (PORT I2 ( 3000 )( 3000 ))
          (PORT I3 ( 3000 )( 3000 ))
          (PORT I4 ( 3000 )( 3000 ))
          (PORT I5 ( 3000 )( 3000 ))
          (PORT I6 ( 1600 )( 1600 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
          (IOPATH I2 O ( 0 )( 0 ))
          (IOPATH I3 O ( 0 )( 0 ))
          (IOPATH I4 O ( 0 )( 0 ))
          (IOPATH I5 O ( 0 )( 0 ))
          (IOPATH I6 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_OR5")
    (INSTANCE state\<4\>_MC\.D2)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 0 )( 0 ))
          (PORT I1 ( 0 )( 0 ))
          (PORT I2 ( 0 )( 0 ))
          (PORT I3 ( 0 )( 0 ))
          (PORT I4 ( 0 )( 0 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
          (IOPATH I2 O ( 0 )( 0 ))
          (IOPATH I3 O ( 0 )( 0 ))
          (IOPATH I4 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_BUF")
    (INSTANCE state\<5\>)
      (DELAY
        (ABSOLUTE
          (IOPATH I O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_XOR2")
    (INSTANCE state\<5\>_MC_tsimcreated_xor_)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 0 )( 0 ))
          (PORT I1 ( 200 )( 200 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_OR2")
    (INSTANCE state\<5\>_MC_tsimcreated_prld_)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 0 )( 0 ))
          (PORT I1 ( 0 )( 0 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_FF")
    (INSTANCE state\<5\>_MC\.REG)
      (DELAY
        (ABSOLUTE
          (IOPATH CLK O ( 700 )( 700 ))
          (IOPATH SET O ( 1500 )( 1500 ))
          (IOPATH RST O ( 1500 )( 1500 ))
        )
      )
      (TIMINGCHECK
        (SETUPHOLD (posedge I) (posedge CLK) (1800)(200))
        (SETUPHOLD (negedge I) (posedge CLK) (1800)(200))
        (SETUPHOLD (posedge CE) (posedge CLK) (0)(0))
        (PERIOD (posedge CLK) (4400))
        (WIDTH (posedge SET) (6000))
        (WIDTH (posedge RST) (6000))
      )
  )
  (CELL (CELLTYPE "X_XOR2")
    (INSTANCE state\<5\>_MC\.D)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 0 )( 0 ))
          (PORT I1 ( 0 )( 0 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND5")
    (INSTANCE state\<5\>_MC\.D2_PT_0)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 3000 )( 3000 ))
          (PORT I1 ( 3000 )( 3000 ))
          (PORT I2 ( 3000 )( 3000 ))
          (PORT I3 ( 3000 )( 3000 ))
          (PORT I4 ( 3000 )( 3000 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
          (IOPATH I2 O ( 0 )( 0 ))
          (IOPATH I3 O ( 0 )( 0 ))
          (IOPATH I4 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND5")
    (INSTANCE state\<5\>_MC\.D2_PT_1)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 3000 )( 3000 ))
          (PORT I1 ( 3000 )( 3000 ))
          (PORT I2 ( 3000 )( 3000 ))
          (PORT I3 ( 3000 )( 3000 ))
          (PORT I4 ( 3000 )( 3000 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
          (IOPATH I2 O ( 0 )( 0 ))
          (IOPATH I3 O ( 0 )( 0 ))
          (IOPATH I4 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_OR2")
    (INSTANCE state\<5\>_MC\.D2)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 0 )( 0 ))
          (PORT I1 ( 0 )( 0 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_BUF")
    (INSTANCE N_PZ_227)
      (DELAY
        (ABSOLUTE
          (IOPATH I O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_BUF")
    (INSTANCE N_PZ_227_MC\.Q)
      (DELAY
        (ABSOLUTE
          (IOPATH I O ( 700 )( 700 ))
        )
      )
  )
  (CELL (CELLTYPE "X_XOR2")
    (INSTANCE N_PZ_227_MC\.D)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 0 )( 0 ))
          (PORT I1 ( 0 )( 0 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND2")
    (INSTANCE N_PZ_227_MC\.D1)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 1100 )( 1100 ))
          (PORT I1 ( 2500 )( 2500 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_BUF")
    (INSTANCE start)
      (DELAY
        (ABSOLUTE
          (IOPATH I O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_OR2")
    (INSTANCE start_MC_tsimcreated_prld_)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 0 )( 0 ))
          (PORT I1 ( 0 )( 0 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_FF")
    (INSTANCE start_MC\.REG)
      (DELAY
        (ABSOLUTE
          (IOPATH CLK O ( 700 )( 700 ))
          (IOPATH SET O ( 1500 )( 1500 ))
          (IOPATH RST O ( 1500 )( 1500 ))
        )
      )
      (TIMINGCHECK
        (SETUPHOLD (posedge I) (posedge CLK) (1800)(200))
        (SETUPHOLD (negedge I) (posedge CLK) (1800)(200))
        (SETUPHOLD (posedge CE) (posedge CLK) (0)(0))
        (PERIOD (posedge CLK) (4400))
        (WIDTH (posedge SET) (6000))
        (WIDTH (posedge RST) (6000))
      )
  )
  (CELL (CELLTYPE "X_INV")
    (INSTANCE start_MC\.REG_tsimcreated_inv_sda_II\/FCLK)
      (DELAY
        (ABSOLUTE
          (IOPATH I O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_XOR2")
    (INSTANCE start_MC\.D)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 0 )( 0 ))
          (PORT I1 ( 0 )( 0 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_BUF")
    (INSTANCE N_PZ_222)
      (DELAY
        (ABSOLUTE
          (IOPATH I O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_BUF")
    (INSTANCE N_PZ_222_MC\.Q)
      (DELAY
        (ABSOLUTE
          (IOPATH I O ( 700 )( 700 ))
        )
      )
  )
  (CELL (CELLTYPE "X_XOR2")
    (INSTANCE N_PZ_222_MC\.D)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 0 )( 0 ))
          (PORT I1 ( 0 )( 0 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND2")
    (INSTANCE N_PZ_222_MC\.D1)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 1100 )( 1100 ))
          (PORT I1 ( 1100 )( 1100 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND6")
    (INSTANCE inport_pre\<1\>_MC\.CE)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 3000 )( 3000 ))
          (PORT I1 ( 3000 )( 3000 ))
          (PORT I2 ( 3000 )( 3000 ))
          (PORT I3 ( 3000 )( 3000 ))
          (PORT I4 ( 3000 )( 3000 ))
          (PORT I5 ( 3000 )( 3000 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
          (IOPATH I2 O ( 0 )( 0 ))
          (IOPATH I3 O ( 0 )( 0 ))
          (IOPATH I4 O ( 0 )( 0 ))
          (IOPATH I5 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND6")
    (INSTANCE inport_pre\<3\>_MC\.CE)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 3000 )( 3000 ))
          (PORT I1 ( 3000 )( 3000 ))
          (PORT I2 ( 3000 )( 3000 ))
          (PORT I3 ( 3000 )( 3000 ))
          (PORT I4 ( 3000 )( 3000 ))
          (PORT I5 ( 3000 )( 3000 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
          (IOPATH I2 O ( 0 )( 0 ))
          (IOPATH I3 O ( 0 )( 0 ))
          (IOPATH I4 O ( 0 )( 0 ))
          (IOPATH I5 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND6")
    (INSTANCE inport_pre\<4\>_MC\.CE)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 3000 )( 3000 ))
          (PORT I1 ( 3000 )( 3000 ))
          (PORT I2 ( 3000 )( 3000 ))
          (PORT I3 ( 3000 )( 3000 ))
          (PORT I4 ( 3000 )( 3000 ))
          (PORT I5 ( 3000 )( 3000 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
          (IOPATH I2 O ( 0 )( 0 ))
          (IOPATH I3 O ( 0 )( 0 ))
          (IOPATH I4 O ( 0 )( 0 ))
          (IOPATH I5 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND6")
    (INSTANCE inport_pre\<5\>_MC\.CE)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 3000 )( 3000 ))
          (PORT I1 ( 3000 )( 3000 ))
          (PORT I2 ( 3000 )( 3000 ))
          (PORT I3 ( 3000 )( 3000 ))
          (PORT I4 ( 3000 )( 3000 ))
          (PORT I5 ( 3000 )( 3000 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
          (IOPATH I2 O ( 0 )( 0 ))
          (IOPATH I3 O ( 0 )( 0 ))
          (IOPATH I4 O ( 0 )( 0 ))
          (IOPATH I5 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND6")
    (INSTANCE inport_pre\<6\>_MC\.CE)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 3000 )( 3000 ))
          (PORT I1 ( 3000 )( 3000 ))
          (PORT I2 ( 3000 )( 3000 ))
          (PORT I3 ( 3000 )( 3000 ))
          (PORT I4 ( 3000 )( 3000 ))
          (PORT I5 ( 3000 )( 3000 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
          (IOPATH I2 O ( 0 )( 0 ))
          (IOPATH I3 O ( 0 )( 0 ))
          (IOPATH I4 O ( 0 )( 0 ))
          (IOPATH I5 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND6")
    (INSTANCE inport_pre\<7\>_MC\.CE)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 3000 )( 3000 ))