i2c_timesim.sdf

在一个32单元CPLD中实现的I2C SLave device

  (CELL (CELLTYPE "X_BUF")
    (INSTANCE portsel\<2\>)
      (DELAY
        (ABSOLUTE
          (IOPATH I O ( 8200 )( 8200 ))
        )
      )
  )
  (CELL (CELLTYPE "X_BUF")
    (INSTANCE portsel\<3\>)
      (DELAY
        (ABSOLUTE
          (IOPATH I O ( 8200 )( 8200 ))
        )
      )
  )
  (CELL (CELLTYPE "X_BUF")
    (INSTANCE portsel\<4\>)
      (DELAY
        (ABSOLUTE
          (IOPATH I O ( 8200 )( 8200 ))
        )
      )
  )
  (CELL (CELLTYPE "X_BUF")
    (INSTANCE portsel\<5\>)
      (DELAY
        (ABSOLUTE
          (IOPATH I O ( 8200 )( 8200 ))
        )
      )
  )
  (CELL (CELLTYPE "X_BUF")
    (INSTANCE portsel\<6\>)
      (DELAY
        (ABSOLUTE
          (IOPATH I O ( 8200 )( 8200 ))
        )
      )
  )
  (CELL (CELLTYPE "X_BUF")
    (INSTANCE portsel\<7\>)
      (DELAY
        (ABSOLUTE
          (IOPATH I O ( 8200 )( 8200 ))
        )
      )
  )
  (CELL (CELLTYPE "X_TRI")
    (INSTANCE scl_n_1)
      (DELAY
        (ABSOLUTE
          (PORT CTL ( 8200 )( 8200 ))
          (IOPATH I O ( 0 )( 0 ))
          (IOPATH CTL O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_TRI")
    (INSTANCE sda_2)
      (DELAY
        (ABSOLUTE
          (PORT CTL ( 8200 )( 8200 ))
          (IOPATH I O ( 0 )( 0 ))
          (IOPATH CTL O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_BUF")
    (INSTANCE outport_MC\.Q)
      (DELAY
        (ABSOLUTE
          (IOPATH I O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_BUF")
    (INSTANCE outport_MC\.Q_tsimrenamed_net_)
      (DELAY
        (ABSOLUTE
          (IOPATH I O ( 700 )( 700 ))
        )
      )
  )
  (CELL (CELLTYPE "X_XOR2")
    (INSTANCE outport_MC\.D)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 0 )( 0 ))
          (PORT I1 ( 0 )( 0 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND2")
    (INSTANCE outport_MC\.D2_PT_0)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 3000 )( 3000 ))
          (PORT I1 ( 3000 )( 3000 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND2")
    (INSTANCE outport_MC\.D2_PT_1)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 1600 )( 1600 ))
          (PORT I1 ( 3000 )( 3000 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND2")
    (INSTANCE outport_MC\.D2_PT_2)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 1600 )( 1600 ))
          (PORT I1 ( 3000 )( 3000 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND2")
    (INSTANCE outport_MC\.D2_PT_3)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 1600 )( 1600 ))
          (PORT I1 ( 3000 )( 3000 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND2")
    (INSTANCE outport_MC\.D2_PT_4)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 1600 )( 1600 ))
          (PORT I1 ( 3000 )( 3000 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND2")
    (INSTANCE outport_MC\.D2_PT_5)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 1600 )( 1600 ))
          (PORT I1 ( 3000 )( 3000 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND2")
    (INSTANCE outport_MC\.D2_PT_6)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 1600 )( 1600 ))
          (PORT I1 ( 3000 )( 3000 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND2")
    (INSTANCE outport_MC\.D2_PT_7)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 1600 )( 1600 ))
          (PORT I1 ( 3000 )( 3000 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND2")
    (INSTANCE outport_MC\.D2_PT_8)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 1600 )( 1600 ))
          (PORT I1 ( 3000 )( 3000 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND2")
    (INSTANCE outport_MC\.D2_PT_9)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 1600 )( 1600 ))
          (PORT I1 ( 3000 )( 3000 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND2")
    (INSTANCE outport_MC\.D2_PT_10)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 1600 )( 1600 ))
          (PORT I1 ( 3000 )( 3000 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND2")
    (INSTANCE outport_MC\.D2_PT_11)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 1600 )( 1600 ))
          (PORT I1 ( 3000 )( 3000 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND2")
    (INSTANCE outport_MC\.D2_PT_12)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 1600 )( 1600 ))
          (PORT I1 ( 3000 )( 3000 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND2")
    (INSTANCE outport_MC\.D2_PT_13)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 1600 )( 1600 ))
          (PORT I1 ( 3000 )( 3000 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND2")
    (INSTANCE outport_MC\.D2_PT_14)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 1600 )( 1600 ))
          (PORT I1 ( 3000 )( 3000 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND2")
    (INSTANCE outport_MC\.D2_PT_15)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 1600 )( 1600 ))
          (PORT I1 ( 3000 )( 3000 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND2")
    (INSTANCE outport_MC\.D2_PT_16)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 1600 )( 1600 ))
          (PORT I1 ( 3000 )( 3000 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND2")
    (INSTANCE outport_MC\.D2_PT_17)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 1600 )( 1600 ))
          (PORT I1 ( 3000 )( 3000 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND2")
    (INSTANCE outport_MC\.D2_PT_18)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 1600 )( 1600 ))
          (PORT I1 ( 3000 )( 3000 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND3")
    (INSTANCE outport_MC\.D2_PT_19)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 1600 )( 1600 ))
          (PORT I1 ( 1600 )( 1600 ))
          (PORT I2 ( 3000 )( 3000 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
          (IOPATH I2 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_OR32")
    (INSTANCE outport_MC\.D2)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 0 )( 0 ))
          (PORT I1 ( 0 )( 0 ))
          (PORT I2 ( 0 )( 0 ))
          (PORT I3 ( 0 )( 0 ))
          (PORT I4 ( 0 )( 0 ))
          (PORT I5 ( 0 )( 0 ))
          (PORT I6 ( 0 )( 0 ))
          (PORT I7 ( 0 )( 0 ))
          (PORT I8 ( 0 )( 0 ))
          (PORT I9 ( 0 )( 0 ))
          (PORT I10 ( 0 )( 0 ))
          (PORT I11 ( 0 )( 0 ))
          (PORT I12 ( 0 )( 0 ))
          (PORT I13 ( 0 )( 0 ))
          (PORT I14 ( 0 )( 0 ))
          (PORT I15 ( 0 )( 0 ))
          (PORT I16 ( 0 )( 0 ))
          (PORT I17 ( 0 )( 0 ))
          (PORT I18 ( 0 )( 0 ))
          (PORT I19 ( 0 )( 0 ))
          (PORT I20 ( 0 )( 0 ))
          (PORT I21 ( 0 )( 0 ))
          (PORT I22 ( 0 )( 0 ))
          (PORT I23 ( 0 )( 0 ))
          (PORT I24 ( 0 )( 0 ))
          (PORT I25 ( 0 )( 0 ))
          (PORT I26 ( 0 )( 0 ))
          (PORT I27 ( 0 )( 0 ))
          (PORT I28 ( 0 )( 0 ))
          (PORT I29 ( 0 )( 0 ))
          (PORT I30 ( 0 )( 0 ))
          (PORT I31 ( 0 )( 0 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
          (IOPATH I2 O ( 0 )( 0 ))
          (IOPATH I3 O ( 0 )( 0 ))
          (IOPATH I4 O ( 0 )( 0 ))
          (IOPATH I5 O ( 0 )( 0 ))
          (IOPATH I6 O ( 0 )( 0 ))
          (IOPATH I7 O ( 0 )( 0 ))
          (IOPATH I8 O ( 0 )( 0 ))
          (IOPATH I9 O ( 0 )( 0 ))
          (IOPATH I10 O ( 0 )( 0 ))
          (IOPATH I11 O ( 0 )( 0 ))
          (IOPATH I12 O ( 0 )( 0 ))
          (IOPATH I13 O ( 0 )( 0 ))
          (IOPATH I14 O ( 0 )( 0 ))
          (IOPATH I15 O ( 0 )( 0 ))
          (IOPATH I16 O ( 0 )( 0 ))
          (IOPATH I17 O ( 0 )( 0 ))
          (IOPATH I18 O ( 0 )( 0 ))
          (IOPATH I19 O ( 0 )( 0 ))
          (IOPATH I20 O ( 0 )( 0 ))
          (IOPATH I21 O ( 0 )( 0 ))
          (IOPATH I22 O ( 0 )( 0 ))
          (IOPATH I23 O ( 0 )( 0 ))
          (IOPATH I24 O ( 0 )( 0 ))
          (IOPATH I25 O ( 0 )( 0 ))
          (IOPATH I26 O ( 0 )( 0 ))
          (IOPATH I27 O ( 0 )( 0 ))
          (IOPATH I28 O ( 0 )( 0 ))
          (IOPATH I29 O ( 0 )( 0 ))
          (IOPATH I30 O ( 0 )( 0 ))
          (IOPATH I31 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND6")
    (INSTANCE inport_pre\<0\>_MC\.CE)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 3000 )( 3000 ))
          (PORT I1 ( 3000 )( 3000 ))
          (PORT I2 ( 3000 )( 3000 ))
          (PORT I3 ( 3000 )( 3000 ))
          (PORT I4 ( 3000 )( 3000 ))
          (PORT I5 ( 3000 )( 3000 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
          (IOPATH I2 O ( 0 )( 0 ))
          (IOPATH I3 O ( 0 )( 0 ))
          (IOPATH I4 O ( 0 )( 0 ))
          (IOPATH I5 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_BUF")
    (INSTANCE state\<0\>)
      (DELAY
        (ABSOLUTE
          (IOPATH I O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_XOR2")
    (INSTANCE state\<0\>_MC_tsimcreated_xor_)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 0 )( 0 ))
          (PORT I1 ( 200 )( 200 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND2")
    (INSTANCE state\<0\>_MC_tsimcreated_set_and_noreset_)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 0 )( 0 ))
          (PORT I1 ( 0 )( 0 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_OR2")
    (INSTANCE state\<0\>_MC_tsimcreated_prld_)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 0 )( 0 ))
          (PORT I1 ( 0 )( 0 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_FF")
    (INSTANCE state\<0\>_MC\.REG)
      (DELAY
        (ABSOLUTE
          (IOPATH CLK O ( 700 )( 700 ))
          (IOPATH SET O ( 1500 )( 1500 ))
          (IOPATH RST O ( 1500 )( 1500 ))
        )
      )
      (TIMINGCHECK
        (SETUPHOLD (posedge I) (posedge CLK) (1800)(200))
        (SETUPHOLD (negedge I) (posedge CLK) (1800)(200))
        (SETUPHOLD (posedge CE) (posedge CLK) (0)(0))
        (PERIOD (posedge CLK) (4400))
        (WIDTH (posedge SET) (6000))
        (WIDTH (posedge RST) (6000))
      )
  )
  (CELL (CELLTYPE "X_XOR2")
    (INSTANCE state\<0\>_MC\.D)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 0 )( 0 ))
          (PORT I1 ( 0 )( 0 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND6")
    (INSTANCE state\<0\>_MC\.D2_PT_0)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 3000 )( 3000 ))
          (PORT I1 ( 3000 )( 3000 ))
          (PORT I2 ( 3000 )( 3000 ))
          (PORT I3 ( 3000 )( 3000 ))
          (PORT I4 ( 3000 )( 3000 ))
          (PORT I5 ( 1600 )( 1600 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
          (IOPATH I2 O ( 0 )( 0 ))
          (IOPATH I3 O ( 0 )( 0 ))
          (IOPATH I4 O ( 0 )( 0 ))
          (IOPATH I5 O ( 0 )( 0 ))
        )
      )
  )
  (CELL (CELLTYPE "X_AND6")
    (INSTANCE state\<0\>_MC\.D2_PT_1)
      (DELAY
        (ABSOLUTE
          (PORT I0 ( 3000 )( 3000 ))
          (PORT I1 ( 3000 )( 3000 ))
          (PORT I2 ( 3000 )( 3000 ))
          (PORT I3 ( 3000 )( 3000 ))
          (PORT I4 ( 3000 )( 3000 ))
          (PORT I5 ( 1600 )( 1600 ))
          (IOPATH I0 O ( 0 )( 0 ))
          (IOPATH I1 O ( 0 )( 0 ))
          (IOPATH I2 O ( 0 )( 0 ))
          (IOPATH I3 O ( 0 )( 0 ))
          (IOPATH I4 O ( 0 )( 0 ))
          (IOPATH I5 O ( 0 )( 0 ))
        )
      )
  )