i2c_timesim.nlf

在一个32单元CPLD中实现的I2C SLave device

Release 9.1i - netgen J.30
Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.

Command Line: netgen -intstyle ise -sdf_anno true -sdf_path netgen/fit
-insert_glbl true -w -dir netgen/fit -ofmt verilog -sim i2c.nga i2c_timesim.v  

Reading design 'i2c.nga' ...
Flattening design ...
Processing design ... 
  Preping design's networks ...
  Preping design's macros ...
Writing Verilog SDF file 'netgen\fit\i2c_timesim.sdf' ...
Writing Verilog netlist file
'D:\PY\Widecom\i2c_x\i2c_10a\netgen\fit\i2c_timesim.v' ...
INFO:NetListWriters:633 - The generated Verilog netlist contains Xilinx SIMPRIM
   simulation primitives and has to be used with SIMPRIM simulation library for
   correct compilation and simulation. 
Number of warnings: 0
Number of info messages: 1
Total memory usage is 53460 kilobytes