hdllib.ref

在一个32单元CPLD中实现的I2C SLave device

MO X_OPAD NULL N:/J.30/rtf/verilog/src/simprims/X_OPAD.v vlg.bin:14013808 1164795457
MO X_ONE NULL N:/J.30/rtf/verilog/src/simprims/X_ONE.v vlg.bin:14013147 1164795457
MO X_OR2 NULL N:/J.30/rtf/verilog/src/simprims/X_OR2.v vlg.bin:14025236 1164795459
MO X_XOR2 NULL N:/J.30/rtf/verilog/src/simprims/X_XOR2.v vlg.bin:2711121 1164795385
MO X_OR3 NULL N:/J.30/rtf/verilog/src/simprims/X_OR3.v vlg.bin:14027253 1164795460
MO X_OR4 NULL N:/J.30/rtf/verilog/src/simprims/X_OR4.v vlg.bin:14050903 1164795461
MO X_OR5 NULL N:/J.30/rtf/verilog/src/simprims/X_OR5.v vlg.bin:14054184 1164795462
MO X_OR6 NULL N:/J.30/rtf/verilog/src/simprims/X_OR6.v vlg.bin:14058097 1164795462
MO X_OR7 NULL N:/J.30/rtf/verilog/src/simprims/X_OR7.v vlg.bin:14062642 1164795463
MO X_OR8 NULL N:/J.30/rtf/verilog/src/simprims/X_OR8.v vlg.bin:14067819 1164795464
MO X_IPAD NULL N:/J.30/rtf/verilog/src/simprims/X_IPAD.v vlg.bin:13216744 1164795439
UD ffsrce NULL N:/J.30/rtf/verilog/src/simprims/X_FF.v vlg.bin:12437014 1164795435
MO X_ZERO NULL N:/J.30/rtf/verilog/src/simprims/X_ZERO.v vlg.bin:2759529 1164795388
MO X_INV NULL N:/J.30/rtf/verilog/src/simprims/X_INV.v vlg.bin:13215360 1164795439
MO X_FF NULL N:/J.30/rtf/verilog/src/simprims/X_FF.v vlg.bin:12423837 1164795435
MO X_BUF NULL N:/J.30/rtf/verilog/src/simprims/X_BUF.v vlg.bin:12047148 1164795427
MO X_BPAD NULL N:/J.30/rtf/verilog/src/simprims/X_BPAD.v vlg.bin:12027957 1164795423
MO X_AND2 NULL N:/J.30/rtf/verilog/src/simprims/X_AND2.v vlg.bin:11973106 1164795417
MO X_AND3 NULL N:/J.30/rtf/verilog/src/simprims/X_AND3.v vlg.bin:11975125 1164795417
MO X_AND4 NULL N:/J.30/rtf/verilog/src/simprims/X_AND4.v vlg.bin:11998779 1164795419
MO X_AND5 NULL N:/J.30/rtf/verilog/src/simprims/X_AND5.v vlg.bin:12002062 1164795420
MO X_AND6 NULL N:/J.30/rtf/verilog/src/simprims/X_AND6.v vlg.bin:12005977 1164795421
MO X_AND7 NULL N:/J.30/rtf/verilog/src/simprims/X_AND7.v vlg.bin:12010524 1164795421
MO X_OR16 NULL N:/J.30/rtf/verilog/src/simprims/X_OR16.v vlg.bin:14014363 1164795458
MO X_OR32 NULL N:/J.30/rtf/verilog/src/simprims/X_OR32.v vlg.bin:14029902 1164795460
MO X_TRI NULL N:/J.30/rtf/verilog/src/simprims/X_TRI.v vlg.bin:2697306 1164795383
MO X_AND16 NULL N:/J.30/rtf/verilog/src/simprims/X_AND16.v vlg.bin:11962231 1164795416