roycpld.map.rpt
来自「这是一个verilog HDL 语言的例子」· RPT 代码 · 共 335 行 · 第 1/2 页
RPT
335 行
; |RoyCPLD ; 260 (48) ; 182 ; 0 ; 22 ; 0 ; 78 (12) ; 37 (3) ; 145 (33) ; 109 (28) ; 0 (0) ; |RoyCPLD ;
; |key:key_check| ; 51 (51) ; 38 ; 0 ; 0 ; 0 ; 13 (13) ; 12 (12) ; 26 (26) ; 20 (20) ; 0 (0) ; |RoyCPLD|key:key_check ;
; |rs232_band_speed:Rs232_band_speed_Send| ; 25 (25) ; 17 ; 0 ; 0 ; 0 ; 8 (8) ; 0 (0) ; 17 (17) ; 16 (16) ; 0 (0) ; |RoyCPLD|rs232_band_speed:Rs232_band_speed_Send ;
; |rs232_band_speed:rs232_band_speed_rec| ; 25 (25) ; 17 ; 0 ; 0 ; 0 ; 8 (8) ; 0 (0) ; 17 (17) ; 16 (16) ; 0 (0) ; |RoyCPLD|rs232_band_speed:rs232_band_speed_rec ;
; |rs232_rec_fun:rs232_receiver| ; 36 (36) ; 25 ; 0 ; 0 ; 0 ; 11 (11) ; 12 (12) ; 13 (13) ; 4 (4) ; 0 (0) ; |RoyCPLD|rs232_rec_fun:rs232_receiver ;
; |rs232_send_fun:Rs232Sender| ; 29 (29) ; 16 ; 0 ; 0 ; 0 ; 13 (13) ; 10 (10) ; 6 (6) ; 0 (0) ; 0 (0) ; |RoyCPLD|rs232_send_fun:Rs232Sender ;
; |sm_led:show_sm_led| ; 46 (46) ; 33 ; 0 ; 0 ; 0 ; 13 (13) ; 0 (0) ; 33 (33) ; 25 (25) ; 0 (0) ; |RoyCPLD|sm_led:show_sm_led ;
+---------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+---------------------------------------------------------------------------------+
; Registers Removed During Synthesis ;
+---------------------------------------+-----------------------------------------+
; Register name ; Reason for Removal ;
+---------------------------------------+-----------------------------------------+
; show_sm_led/SM_CS2_r ; Merged with show_sm_led/SM_CS1_r ;
; Rs232Sender/tx_en ; Merged with Rs232Sender/band_start_r ;
; rs232_receiver/Received_Byte_Flag_r ; Merged with rs232_receiver/band_start_r ;
; led_d2_r ; Merged with data1_r[0] ;
; data1_r[2] ; Lost fanout ;
; data1_r[3] ; Lost fanout ;
; Total Number of Removed Registers = 6 ; ;
+---------------------------------------+-----------------------------------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 182 ;
; Number of registers using Synchronous Clear ; 109 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 178 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 28 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+---------------------------------------------------+
; Inverted Register Statistics ;
+-----------------------------------------+---------+
; Inverted Register ; Fan out ;
+-----------------------------------------+---------+
; rs232_send_fun:Rs232Sender|rs232_tx_r ; 2 ;
; key:key_check|led_d0_r ; 2 ;
; led_d3_r ; 2 ;
; data1_r[2]~396 ; 2 ;
; key:key_check|key_state_now[0] ; 2 ;
; key:key_check|key_state_pre[0] ; 1 ;
; key:key_check|key_state_now[1] ; 2 ;
; key:key_check|key_state_now[3] ; 2 ;
; key:key_check|key_state_pre[1] ; 1 ;
; key:key_check|key_state_pre[3] ; 1 ;
; key:key_check|key_state_now[2] ; 2 ;
; key:key_check|key_state_pre[2] ; 1 ;
; Total number of inverted registers = 12 ; ;
+-----------------------------------------+---------+
+-----------------------------------------------+
; Gate-level Retiming ;
+----------------+------------+-----------------+
; Register Name ; Clock Name ; Created/Deleted ;
+----------------+------------+-----------------+
; data1_r[2] ; Clk ; Deleted ;
; data1_r[3] ; Clk ; Deleted ;
; data1_r[2]~396 ; Clk ; Created ;
; data1_r[3]~397 ; Clk ; Created ;
; data1_r[3]~398 ; Clk ; Created ;
; data1_r[3]~399 ; Clk ; Created ;
+----------------+------------+-----------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------+
; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |RoyCPLD|rs232_rec_fun:rs232_receiver|num[3] ;
; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |RoyCPLD|rs232_send_fun:Rs232Sender|num[0] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------+
+-----------------------------------------------------------------+
; Parameter Settings for User Entity Instance: sm_led:show_sm_led ;
+----------------+---------+--------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+---------+--------------------------------------+
; seg0 ; 0111111 ; Unsigned Binary ;
; seg1 ; 0000110 ; Unsigned Binary ;
; seg2 ; 1011011 ; Unsigned Binary ;
; seg3 ; 1001111 ; Unsigned Binary ;
; seg4 ; 1100110 ; Unsigned Binary ;
; seg5 ; 1101101 ; Unsigned Binary ;
; seg6 ; 1111101 ; Unsigned Binary ;
; seg7 ; 0000111 ; Unsigned Binary ;
; seg8 ; 1111111 ; Unsigned Binary ;
; seg9 ; 1101111 ; Unsigned Binary ;
; sega ; 1110111 ; Unsigned Binary ;
; segb ; 1111100 ; Unsigned Binary ;
; segc ; 0111001 ; Unsigned Binary ;
; segd ; 1011110 ; Unsigned Binary ;
; sege ; 1111001 ; Unsigned Binary ;
; segf ; 1110001 ; Unsigned Binary ;
; cnt_limit ; 2000 ; Signed Integer ;
; cnt_limit_by2 ; 1000 ; Signed Integer ;
+----------------+---------+--------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
Info: Processing started: Fri Feb 06 14:48:40 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RoyCPLD -c RoyCPLD
Info: Found 1 design units, including 1 entities, in source file rs232_send_fun.v
Info: Found entity 1: rs232_send_fun
Info: Found 1 design units, including 1 entities, in source file RoyCPLD.v
Info: Found entity 1: RoyCPLD
Info: Found 1 design units, including 1 entities, in source file led.v
Info: Found entity 1: sm_led
Info: Found 1 design units, including 1 entities, in source file rs232_speed.v
Info: Found entity 1: rs232_band_speed
Info: Found 1 design units, including 1 entities, in source file rs232_rec_fun.v
Info: Found entity 1: rs232_rec_fun
Info: Found 1 design units, including 1 entities, in source file key.v
Info: Found entity 1: key
Info: Elaborating entity "RoyCPLD" for the top level hierarchy
Warning (10036): Verilog HDL or VHDL warning at RoyCPLD.v(37): object "second_r" assigned a value but never read
Info: Elaborating entity "rs232_band_speed" for hierarchy "rs232_band_speed:rs232_band_speed_rec"
Info: Elaborating entity "rs232_rec_fun" for hierarchy "rs232_rec_fun:rs232_receiver"
Info: Elaborating entity "rs232_send_fun" for hierarchy "rs232_send_fun:Rs232Sender"
Info: Elaborating entity "sm_led" for hierarchy "sm_led:show_sm_led"
Info: Elaborating entity "key" for hierarchy "key:key_check"
Info: Duplicate registers merged to single register
Info: Duplicate register "sm_led:show_sm_led|SM_CS2_r" merged to single register "sm_led:show_sm_led|SM_CS1_r", power-up level changed
Info: Duplicate register "rs232_send_fun:Rs232Sender|tx_en" merged to single register "rs232_send_fun:Rs232Sender|band_start_r"
Info: Duplicate register "rs232_rec_fun:rs232_receiver|Received_Byte_Flag_r" merged to single register "rs232_rec_fun:rs232_receiver|band_start_r"
Info: Duplicate registers merged to single register
Info: Duplicate register "led_d2_r" merged to single register "data1_r[0]"
Info: Performing gate-level register retiming
Info: Not allowed to move 23 registers
Info: Not allowed to move at least 9 registers because they are in a sequence of registers directly fed by input pins
Info: Not allowed to move at least 14 registers because they feed output pins directly
Info: Quartus II software applied gate-level register retiming to 1 clock domains
Info: Quartus II software applied gate-level register retiming to clock "Clk": created 4 new registers, removed 2 registers, left 69 registers untouched
Info: Registers with preset signals will power-up high
Info: 2 registers lost all their fanouts during netlist optimizations. The first 2 are displayed below.
Info: Register "data1_r[2]" lost all its fanouts during netlist optimizations.
Info: Register "data1_r[3]" lost all its fanouts during netlist optimizations.
Info: Implemented 282 device resources after synthesis - the final resource count might be different
Info: Implemented 7 input pins
Info: Implemented 15 output pins
Info: Implemented 260 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
Info: Allocated 124 megabytes of memory during processing
Info: Processing ended: Fri Feb 06 14:48:43 2009
Info: Elapsed time: 00:00:03
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