roycpld.map.summary

来自「这是一个verilog HDL 语言的例子」· SUMMARY 代码 · 共 10 行

Analysis & Synthesis Status : Successful - Fri Feb 06 14:48:43 2009
Quartus II Version : 7.0 Build 33 02/05/2007 SJ Full Version
Revision Name : RoyCPLD
Top-level Entity Name : RoyCPLD
Family : MAX II
Total logic elements : 260
Total pins : 22
Total virtual pins : 0
UFM blocks : 0