roycpld.tan.summary

这是一个verilog HDL 语言的例子

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 5.268 ns
From           : rs232_rx
To             : rs232_rec_fun:rs232_receiver|rec_tempdata_r[6]
From Clock     : --
To Clock       : Clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 9.813 ns
From           : rs232_send_fun:Rs232Sender|rs232_tx_r
To             : rs232_tx
From Clock     : Clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -2.416 ns
From           : sw1
To             : key:key_check|key_state_now[1]
From Clock     : --
To Clock       : Clk
Failed Paths   : 0

Type           : Clock Setup: 'Clk'
Slack          : -0.172 ns
Required Time  : 100.00 MHz ( period = 10.000 ns )
Actual Time    : 98.31 MHz ( period = 10.172 ns )
From           : led_cnt_r[25]
To             : led_cnt_r[27]
From Clock     : Clk
To Clock       : Clk
Failed Paths   : 76

Type           : Clock Hold: 'Clk'
Slack          : 1.078 ns
Required Time  : 100.00 MHz ( period = 10.000 ns )
Actual Time    : N/A
From           : data1_r[3]~397
To             : data1_r[3]~397
From Clock     : Clk
To Clock       : Clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 76

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