roycpld.fit.summary

这是一个verilog HDL 语言的例子

Fitter Status : Successful - Fri Feb 06 14:49:00 2009
Quartus II Version : 7.0 Build 33 02/05/2007 SJ Full Version
Revision Name : RoyCPLD
Top-level Entity Name : RoyCPLD
Family : MAX II
Device : EPM240T100C5
Timing Models : Final
Total logic elements : 225 / 240 ( 94 % )
Total pins : 22 / 80 ( 28 % )
Total virtual pins : 0
UFM blocks : 0 / 1 ( 0 % )