roycpld.map.smsg

来自「这是一个verilog HDL 语言的例子」· SMSG 代码 · 共 22 行

Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Fri Jan 23 03:22:24 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RoyCPLD -c RoyCPLD
Info: Found 1 design units, including 1 entities, in source file rs232_send_fun.v
    Info: Found entity 1: rs232_send_fun
Info: Found 1 design units, including 1 entities, in source file RoyCPLD.v
    Info: Found entity 1: RoyCPLD
Info: Found 1 design units, including 1 entities, in source file led.v
    Info: Found entity 1: sm_led
Info: Found 1 design units, including 1 entities, in source file rs232_speed.v
    Info: Found entity 1: rs232_band_speed
Info: Found 1 design units, including 1 entities, in source file rs232_rec_fun.v
    Info: Found entity 1: rs232_rec_fun
Error (10161): Verilog HDL error at rs232_send_fun.v(75): object "bps_start_r" is not declared File: D:/CPLD Prj/RoyCPLD/rs232_send_fun.v Line: 75
Error (10161): Verilog HDL error at rs232_send_fun.v(77): object "bps_start_r" is not declared File: D:/CPLD Prj/RoyCPLD/rs232_send_fun.v Line: 77
Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 0 warnings
    Info: Allocated 116 megabytes of memory during processing
    Error: Processing ended: Fri Jan 23 03:22:25 2009
    Error: Elapsed time: 00:00:01