test_createspi.v

Verilog HDL的程式

module test_createspi(clk, low, high, scko, mosio, dirz, write);

input clk;
input low;
input high;
output scko;
output mosio;
output dirz;
output write;

wire [1:0]addr;
wire [7:0]dout;
wire scko;
wire irq;
wire write;

spidatasent U1(	.clk(clk), .scko(scko), .irq(irq), .write(write), .address(addr), .dout(dout),
				.dirz(dirz));
vspi U2(.clk(clk), .addr(addr), .datain(dout), .write(write), .chip_sel(write), .slvsel(low),
		.irq(irq), .mosio(mosio), .scko(scko), .rst(high), .scki(low), .misoi(low));

endmodule