spidatasent.v

Verilog HDL的程式

module spidatasent(clk, scko, irq, write, address, dout, dirz);

input clk;
input scko;
input irq;

output write;
output [1:0]address;
output [7:0]dout;
output dirz;
//output [3:0]co;

reg xwrite;
reg xdirz;
reg [1:0]xaddress;
reg [7:0]xdout;

reg [3:0]count;
reg [7:0]init;


assign write=~xwrite;
assign address=xaddress;
assign dout=xdout;
assign dirz=~xdirz;

//assign co=count;
always @(posedge clk)
begin
	if(init==8'd0)
	begin
		xwrite<=1'b1;
		xaddress<=2'b01;
		xdout<=8'h82;
		init<=8'd1;
		xdirz<=1'b0;
	end
	else if((init==8'd1) || (init==8'd48) || (init==8'd93))
	begin
		xdirz<=1'b1;
		init<=init+1;
		xwrite<=1'b0;
	end
	else if(init == 8'd2) //byte 0 sent(red)
	begin
		xdirz<=1'b0;
		if(count==4'd0)
		begin
			xwrite<=1'b1;
			xaddress<=2'b00;
			xdout<=8'h00;
			init<=8'd3;
		end
		else
		begin
			xwrite<=1'b0;
		end
	end
	else if((init==8'd4) || (init==8'd6) || (init==8'd8) || (init==8'd10) || (init==8'd12) || (init==8'd14) ||
			(init==8'd16) || (init==8'd18) || (init==8'd20) || (init==8'd22) || (init==8'd24) || (init==8'd26) ||
			(init==8'd28) || (init==8'd30) || (init==8'd32) || (init==8'd34) || (init==8'd36) || (init==8'd38) ||
			(init==8'd40) || (init==8'd42) || (init==8'd44) || (init==8'd46)) //2~22
	begin
		xdirz<=1'b0;
		if(count==4'd0)
		begin
			xwrite<=1'b1;
			xaddress<=2'b00;
			xdout<=8'h66;
			init<=init+1;
		end
		else
		begin
			xwrite<=1'b0;
		end	
	end
	else if((init==8'd3) || (init==8'd5) || (init==8'd7) || (init==8'd9) || (init==8'd11) || (init==8'd13) ||
			(init==8'd15) || (init==8'd17) || (init==8'd19) || (init==8'd21) || (init==8'd23) || (init==8'd25) ||
			(init==8'd27) || (init==8'd29) || (init==8'd31) || (init==8'd33) || (init==8'd35) || (init==8'd37) ||
			(init==8'd39) || (init==8'd41) || (init==8'd43) || (init==8'd45) || (init==8'd47) || (init==8'd50) ||
			(init==8'd52) || (init==8'd54) || (init==8'd56) || (init==8'd58) || (init==8'd60) || (init==8'd62) ||
			(init==8'd64) || (init==8'd66) || (init==8'd68) || (init==8'd70) || (init==8'd72) || (init==8'd74) ||
			(init==8'd76) || (init==8'd78) || (init==8'd80) || (init==8'd82) || (init==8'd84) || (init==8'd86) ||
			(init==8'd88) || (init==8'd90) || (init==8'd92) || (init==8'd95) || (init==8'd97) || (init==8'd99) ||
			(init==8'd101) || (init==8'd103) || (init==8'd105) || (init==8'd107) || (init==8'd109) || (init==8'd111) ||
			(init==8'd113) || (init==8'd115) || (init==8'd117) || (init==8'd119) || (init==8'd121) || (init==8'd123) ||
			(init==8'd125) || (init==8'd127) || (init==8'd129) || (init==8'd131) || (init==8'd133) ||	(init==8'd135) ||
			(init==8'd137) || (init==8'd139))
	begin
		xdirz<=1'b0;
		if(count>=4'd8)
		begin
			init<=init+1;
			xwrite<=1'b1;
		end
		else
		begin
			xwrite<=1'b1;
		end
	end
	else if(init == 8'd49)//byte 0(greed)
	begin
		xdirz<=1'b0;
		if(count==4'd0)
		begin
			xwrite<=1'b1;
			xaddress<=2'b00;
			xdout<=8'h10;
			init<=init+1;
		end
		else
		begin
			xwrite<=1'b0;
		end
	end
	else if((init==8'd51) || (init==8'd53) || (init==8'd55) || (init==8'd57) || (init==8'd59) || (init==8'd61) ||
			(init==8'd63) || (init==8'd65) || (init==8'd67) || (init==8'd69) || (init==8'd71) || (init==8'd73) ||
			(init==8'd75) || (init==8'd77) || (init==8'd79) || (init==8'd81) || (init==8'd83) || (init==8'd85) ||
			(init==8'd87) || (init==8'd89) || (init==8'd90) || (init==8'd91)) //2~22
	begin
		xdirz<=1'b0;
		if(count==4'd0)
		begin
			xwrite<=1'b1;
			xaddress<=2'b00;
			xdout<=8'h55;
			init<=init+1;
		end
		else
		begin
			xwrite<=1'b0;
		end	
	end
	else if(init==8'd94)//byte 0(blue)
	begin
		xdirz<=1'b0;
		if(count==4'd0)
		begin
			xwrite<=1'b1;
			xaddress<=2'b00;
			xdout<=8'h20;
			init<=init+1;
		end
		else
		begin
			xwrite<=1'b0;
		end
	end
	else if((init==8'd96) || (init==8'd98) || (init==8'd100) || (init==8'd102) || (init==8'd104) || (init==8'd106) ||
			(init==8'd108) || (init==8'd110) || (init==8'd112) || (init==8'd114) || (init==8'd116) || (init==8'd118) ||
			(init==8'd120) || (init==8'd122) || (init==8'd124) || (init==8'd126) || (init==8'd128) || (init==8'd130) ||
			(init==8'd132) || (init==8'd134) || (init==8'd136) || (init==8'd138)) //2~22
	begin
		xdirz<=1'b0;
		if(count==4'd0)
		begin
			xwrite<=1'b1;
			xaddress<=2'b00;
			xdout<=8'h77;
			init<=init+1;
		end
		else
		begin
			xwrite<=1'b0;
		end	
	end
	else if(init==8'd140)
	begin
		xwrite<=1'b0;
		xdirz<=1'b0;
		init<=8'd1;
	end
	//end
end

always @(posedge scko or posedge irq)
begin
	if(irq==1'b1)
	begin
		count<=4'd0;
	end
	else
	begin
		count<=count+1;
	end
end
endmodule