📄 test_createspi.rpt
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- 2 - A 14 DFFE + 0 4 0 4 |spidatasent:U1|xdout2 (|spidatasent:U1|:2450)
- 6 - A 15 DFFE + 0 4 0 4 |spidatasent:U1|xdout1 (|spidatasent:U1|:2451)
- 7 - A 24 DFFE + 0 3 0 2 |spidatasent:U1|xdout0 (|spidatasent:U1|:2452)
- 5 - A 24 AND2 s 0 2 0 3 |spidatasent:U1|~2488~1
- 6 - B 07 AND2 s 0 2 0 5 |spidatasent:U1|~2488~2
- 8 - B 21 AND2 s 0 2 0 5 |spidatasent:U1|~2488~3
- 6 - B 05 AND2 s 0 2 0 3 |spidatasent:U1|~2488~4
- 5 - B 05 AND2 s 0 4 0 1 |spidatasent:U1|~2488~5
- 8 - B 05 DFFE + 0 4 1 1 |spidatasent:U1|xdirz (|spidatasent:U1|:2492)
- 1 - A 08 OR2 0 4 0 2 |vspi:U2|lpm_add_sub:869|addcore:adder|pcarry3
- 4 - A 08 OR2 0 3 0 1 |vspi:U2|lpm_add_sub:869|addcore:adder|:76
- 2 - A 08 OR2 0 4 0 1 |vspi:U2|lpm_add_sub:869|addcore:adder|:77
- 7 - A 01 OR2 ! 0 3 0 7 |vspi:U2|:79
- 1 - A 12 DFFE + 1 2 0 1 |vspi:U2|ctl_reg7 (|vspi:U2|:121)
- 4 - A 04 DFFE + 1 2 0 3 |vspi:U2|ctl_reg6 (|vspi:U2|:122)
- 2 - A 04 DFFE + 1 2 0 3 |vspi:U2|ctl_reg5 (|vspi:U2|:123)
- 7 - A 13 DFFE + 1 2 0 3 |vspi:U2|ctl_reg4 (|vspi:U2|:124)
- 8 - A 03 DFFE + 1 2 0 2 |vspi:U2|ctl_reg3 (|vspi:U2|:125)
- 3 - A 14 DFFE + 1 2 0 1 |vspi:U2|ctl_reg2 (|vspi:U2|:126)
- 1 - A 13 DFFE + 1 2 0 8 |vspi:U2|ctl_reg1 (|vspi:U2|:127)
- 4 - A 06 AND2 0 2 0 5 |vspi:U2|:132
- 1 - A 01 AND2 0 3 0 3 |vspi:U2|:164
- 6 - A 06 DFFE + 1 2 0 1 |vspi:U2|ssel7 (|vspi:U2|:206)
- 2 - A 11 DFFE + 1 2 0 1 |vspi:U2|ssel6 (|vspi:U2|:207)
- 1 - A 11 DFFE + 1 2 0 1 |vspi:U2|ssel5 (|vspi:U2|:208)
- 1 - A 06 AND2 ! 0 3 0 6 |vspi:U2|:224
- 6 - A 04 OR2 0 3 0 1 |vspi:U2|:296
- 5 - A 04 OR2 0 3 0 1 |vspi:U2|:297
- 3 - A 04 OR2 0 3 0 3 |vspi:U2|:298
- 7 - A 04 OR2 0 4 0 1 |vspi:U2|:308
- 8 - A 04 DFFE + 0 2 0 2 |vspi:U2|dvd_ctr4 (|vspi:U2|:323)
- 3 - A 08 DFFE + 0 4 0 2 |vspi:U2|dvd_ctr3 (|vspi:U2|:324)
- 5 - A 08 DFFE + 0 4 0 3 |vspi:U2|dvd_ctr2 (|vspi:U2|:325)
- 7 - A 08 DFFE + 0 3 0 3 |vspi:U2|dvd_ctr1 (|vspi:U2|:326)
- 6 - A 08 DFFE + 0 1 0 4 |vspi:U2|dvd_ctr0 (|vspi:U2|:327)
- 1 - A 04 OR2 ! 0 2 0 7 |vspi:U2|:328
- 5 - A 06 DFFE + 0 1 0 2 |vspi:U2|tx_start_r1 (|vspi:U2|:341)
- 1 - A 02 DFFE + 0 3 0 3 |vspi:U2|dvd2 (|vspi:U2|:354)
- 2 - A 03 DFFE + 1 1 0 1 |vspi:U2|sck_r1 (|vspi:U2|:363)
- 5 - A 02 DFFE + 0 1 0 3 |vspi:U2|sck_r2 (|vspi:U2|:365)
- 6 - A 02 DFFE + 0 1 0 2 |vspi:U2|sck_r3 (|vspi:U2|:367)
- 3 - A 02 OR2 ! 0 4 0 11 |vspi:U2|:370
- 2 - A 02 OR2 ! 0 3 0 2 |vspi:U2|:371
- 7 - A 06 OR2 0 4 0 1 |vspi:U2|:384
- 6 - A 11 OR2 0 3 0 1 |vspi:U2|:385
- 3 - A 11 OR2 0 2 0 1 |vspi:U2|:386
- 8 - A 06 DFFE + 1 3 0 2 |vspi:U2|bit_ctr2 (|vspi:U2|:399)
- 4 - A 11 DFFE + 1 3 0 3 |vspi:U2|bit_ctr1 (|vspi:U2|:400)
- 5 - A 11 DFFE + 1 3 0 4 |vspi:U2|bit_ctr0 (|vspi:U2|:401)
- 2 - A 06 OR2 ! 0 4 0 3 |vspi:U2|:410
- 3 - A 06 DFFE + 1 2 0 3 |vspi:U2|tx_run (|vspi:U2|:425)
- 3 - A 05 DFFE + 1 0 0 1 |vspi:U2|slvsel_r1 (|vspi:U2|:429)
- 4 - A 05 DFFE + 0 1 0 2 |vspi:U2|slvsel_r2 (|vspi:U2|:431)
- 1 - A 05 DFFE + 0 1 0 2 |vspi:U2|slvsel_r3 (|vspi:U2|:433)
- 3 - A 01 AND2 s 0 2 0 1 |vspi:U2|~435~1
- 8 - A 01 AND2 0 4 0 10 |vspi:U2|:435
- 8 - A 02 OR2 ! 0 3 0 1 |vspi:U2|:463
- 4 - A 02 OR2 s ! 0 3 0 2 |vspi:U2|~464~1
- 7 - A 02 OR2 ! 0 3 0 1 |vspi:U2|:465
- 3 - A 13 OR2 1 3 0 1 |vspi:U2|:475
- 5 - A 13 OR2 0 3 0 1 |vspi:U2|:486
- 6 - A 13 DFFE + 1 3 0 3 |vspi:U2|shift_negative_edge (|vspi:U2|:491)
- 2 - A 13 OR2 1 3 0 1 |vspi:U2|:497
- 8 - A 16 OR2 0 3 0 1 |vspi:U2|:519
- 6 - A 16 OR2 0 3 0 1 |vspi:U2|:520
- 4 - A 16 OR2 0 3 0 1 |vspi:U2|:521
- 6 - A 03 OR2 0 3 0 1 |vspi:U2|:522
- 3 - A 03 OR2 0 3 0 1 |vspi:U2|:523
- 2 - A 20 OR2 0 3 0 1 |vspi:U2|:524
- 3 - A 16 OR2 0 3 0 1 |vspi:U2|:525
- 1 - A 19 OR2 0 3 0 1 |vspi:U2|:526
- 1 - A 16 DFFE + 1 3 0 3 |vspi:U2|shift_reg7 (|vspi:U2|:559)
- 7 - A 16 DFFE + 1 3 0 2 |vspi:U2|shift_reg6 (|vspi:U2|:560)
- 5 - A 16 DFFE + 1 3 0 2 |vspi:U2|shift_reg5 (|vspi:U2|:561)
- 1 - A 03 DFFE + 1 3 0 2 |vspi:U2|shift_reg4 (|vspi:U2|:562)
- 4 - A 03 DFFE + 1 3 0 2 |vspi:U2|shift_reg3 (|vspi:U2|:563)
- 1 - A 20 DFFE + 1 3 0 2 |vspi:U2|shift_reg2 (|vspi:U2|:564)
- 2 - A 16 DFFE + 1 3 0 2 |vspi:U2|shift_reg1 (|vspi:U2|:565)
- 8 - A 19 DFFE + 1 3 0 2 |vspi:U2|shift_reg0 (|vspi:U2|:566)
- 2 - A 05 DFFE + 1 3 0 1 |vspi:U2|irq_flag (|vspi:U2|:587)
- 3 - A 12 OR2 ! 0 2 0 4 |vspi:U2|:795
- 8 - A 13 OR2 0 3 0 1 |vspi:U2|:809
- 4 - A 13 AND2 0 3 1 0 |vspi:U2|:856
- 5 - A 03 OR2 0 2 1 4 |vspi:U2|:861
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\program\fpga\led driver\test_createspi.rpt
test_createspi
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 16/ 96( 16%) 23/ 48( 47%) 26/ 48( 54%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
B: 34/ 96( 35%) 15/ 48( 31%) 23/ 48( 47%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\program\fpga\led driver\test_createspi.rpt
test_createspi
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 57 clk
LCELL 5 |vspi:U2|:861
Device-Specific Information: d:\program\fpga\led driver\test_createspi.rpt
test_createspi
** CLEAR SIGNALS **
Type Fan-out Name
LCELL 4 |vspi:U2|:795
Device-Specific Information: d:\program\fpga\led driver\test_createspi.rpt
test_createspi
** EQUATIONS **
clk : INPUT;
high : INPUT;
low : INPUT;
-- Node name is 'dirz'
-- Equation name is 'dirz', type is output
dirz = !_LC8_B5;
-- Node name is 'mosio'
-- Equation name is 'mosio', type is output
mosio = _LC4_A13;
-- Node name is 'scko'
-- Equation name is 'scko', type is output
scko = _LC5_A3;
-- Node name is 'write'
-- Equation name is 'write', type is output
write = !_LC7_B5;
-- Node name is '|spidatasent:U1|:84' = '|spidatasent:U1|count0'
-- Equation name is '_LC5_A12', type is buried
_LC5_A12 = DFFE(!_LC5_A12, _LC5_A3, !_LC3_A12, VCC, VCC);
-- Node name is '|spidatasent:U1|:83' = '|spidatasent:U1|count1'
-- Equation name is '_LC6_A12', type is buried
_LC6_A12 = DFFE( _EQ001, _LC5_A3, !_LC3_A12, VCC, VCC);
_EQ001 = _LC5_A12 & !_LC6_A12
# !_LC5_A12 & _LC6_A12;
-- Node name is '|spidatasent:U1|:82' = '|spidatasent:U1|count2'
-- Equation name is '_LC7_A12', type is buried
_LC7_A12 = DFFE( _EQ002, _LC5_A3, !_LC3_A12, VCC, VCC);
_EQ002 = !_LC5_A12 & _LC7_A12
# !_LC6_A12 & _LC7_A12
# _LC5_A12 & _LC6_A12 & !_LC7_A12;
-- Node name is '|spidatasent:U1|:81' = '|spidatasent:U1|count3'
-- Equation name is '_LC4_A12', type is buried
_LC4_A12 = DFFE( _EQ003, _LC5_A3, !_LC3_A12, VCC, VCC);
_EQ003 = _LC4_A12 & !_LC5_A12
# _LC4_A12 & !_LC6_A12
# _LC4_A12 & !_LC7_A12
# !_LC4_A12 & _LC5_A12 & _LC6_A12 & _LC7_A12;
-- Node name is '|spidatasent:U1|:1910' = '|spidatasent:U1|init0'
-- Equation name is '_LC3_B2', type is buried
_LC3_B2 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = !_LC6_B19 & _LC8_B2
# _LC2_B13
# _LC6_B22;
-- Node name is '|spidatasent:U1|:1909' = '|spidatasent:U1|init1'
-- Equation name is '_LC6_B16', type is buried
_LC6_B16 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = !_LC6_B19 & !_LC6_B22 & _LC7_B16
# _LC6_B19 & !_LC6_B22 & _LC8_B16;
-- Node name is '|spidatasent:U1|:1908' = '|spidatasent:U1|init2'
-- Equation name is '_LC7_B20', type is buried
_LC7_B20 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = _LC6_B20 & !_LC6_B22
# _LC6_B19 & !_LC6_B22 & _LC8_B20;
-- Node name is '|spidatasent:U1|:1907' = '|spidatasent:U1|init3'
-- Equation name is '_LC2_B21', type is buried
_LC2_B21 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = !_LC6_B22 & _LC7_B21
# _LC4_B13 & _LC6_B19 & !_LC6_B22;
-- Node name is '|spidatasent:U1|:1906' = '|spidatasent:U1|init4'
-- Equation name is '_LC6_B6', type is buried
_LC6_B6 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = !_LC6_B22 & _LC7_B6
# _LC6_B19 & !_LC6_B22 & _LC8_B6;
-- Node name is '|spidatasent:U1|:1905' = '|spidatasent:U1|init5'
-- Equation name is '_LC7_B3', type is buried
_LC7_B3 = DFFE( _EQ009, GLOBAL( clk), VCC, VCC, VCC);
_EQ009 = _LC6_B3 & !_LC6_B22
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