📄 mem_interface_top.ucf
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############################################################################
# I/O STANDARDS #
############################################################################
NET "cntrl0_ddr1_address(*)" IOSTANDARD = SSTL2_II;
NET "cntrl0_ddr1_ba(*)" IOSTANDARD = SSTL2_II;
NET "cntrl0_ddr1_dm(*)" IOSTANDARD = SSTL2_II;
NET "cntrl0_ddr1_rasb" IOSTANDARD = SSTL2_II;
NET "cntrl0_ddr1_casb" IOSTANDARD = SSTL2_II;
NET "cntrl0_ddr1_web" IOSTANDARD = SSTL2_II;
NET "cntrl0_ddr1_csb" IOSTANDARD = SSTL2_II;
NET "cntrl0_ddr1_cke" IOSTANDARD = SSTL2_II;
NET "cntrl0_ddr1_clk*" IOSTANDARD = SSTL2_II;
NET "cntrl0_ddr1_clk*b" IOSTANDARD = SSTL2_II;
NET "cntrl0_ddr1_dq(*)" IOSTANDARD = SSTL2_II;
NET "cntrl0_ddr1_dqs(*)" IOSTANDARD = SSTL2_II;
NET "cntrl0_rst_dqs_div_in" IOSTANDARD = SSTL2_II;
NET "cntrl0_rst_dqs_div_out" IOSTANDARD = SSTL2_II;
#NET "dimm_clk*" IOSTANDARD = SSTL2_II;
#NET "dimm_clk*b" IOSTANDARD = SSTL2_II;
NET "SYS_CLK*" IOSTANDARD = LVDS_25;
#NET "dummy(*)" IOSTANDARD = SSTL2_II;
NET "reset_in" LOC = "A13"; # resetN
NET "SYS_CLKb" LOC = "AE14"; # CLK.LVDSN
NET "SYS_CLK" LOC = "AF14"; # CLK.LVDSP
#NET "SYS_CLKb" LOC = "G13"; # CLK.LVDSP # on board clk
#NET "SYS_CLK" LOC = "F13"; # CLK.LVDSN # on board clk
#NET "display1(0)" LOC = "AE5"; # DISPLAY1A
#NET "display1(1)" LOC = "AD5"; # DISPLAY1B
#NET "display1(2)" LOC = "AD6"; # DISPLAY1C
#NET "display1(3)" LOC = "AC6"; # DISPLAY1D
#NET "display1(4)" LOC = "AF6"; # DISPLAY1E
#NET "display1(5)" LOC = "AE6"; # DISPLAY1F
#NET "display1(6)" LOC = "AC7"; # DISPLAY1G
#NET "JP1_header(0)" LOC = "F12";
#NET "JP1_header(1)" LOC = "H13";
#NET "JP1_header(2)" LOC = "G12";
#NET "JP1_header(3)" LOC = "H12";
#NET "JP1_header(4)" LOC = "B11";
#NET "JP1_header(5)" LOC = "D11";
#NET "JP1_header(6)" LOC = "E11";
#NET "JP1_header(7)" LOC = "F11";
#NET "JP2_header(0)" LOC = "G11";
#NET "JP2_header(1)" LOC = "A10";
#NET "JP2_header(2)" LOC = "B10";
#NET "JP2_header(3)" LOC = "H11";
#NET "JP2_header(4)" LOC = "C10";
#NET "JP2_header(5)" LOC = "D10";
#NET "JP2_header(6)" LOC = "E10";
#NET "JP2_header(7)" LOC = "F10";
NET "cntrl0_led_error_output1" LOC = "M7";
NET "cntrl0_ddr1_address(0)" LOC = "E7" ;
NET "cntrl0_ddr1_address(1)" LOC = "A6" ;
NET "cntrl0_ddr1_address(10)" LOC = "C4" ;
NET "cntrl0_ddr1_address(11)" LOC = "A3" ;
NET "cntrl0_ddr1_address(12)" LOC = "D2" ;
NET "cntrl0_ddr1_address(2)" LOC = "B6" ;
NET "cntrl0_ddr1_address(3)" LOC = "C6" ;
NET "cntrl0_ddr1_address(4)" LOC = "D6" ;
NET "cntrl0_ddr1_address(5)" LOC = "E6" ;
NET "cntrl0_ddr1_address(6)" LOC = "A5" ;
NET "cntrl0_ddr1_address(7)" LOC = "B5" ;
NET "cntrl0_ddr1_address(8)" LOC = "C5" ;
NET "cntrl0_ddr1_address(9)" LOC = "B4" ;
NET "cntrl0_ddr1_ba(0)" LOC = "P5" ;
NET "cntrl0_ddr1_ba(1)" LOC = "H2" ;
NET "cntrl0_ddr1_casb" LOC = "N5" ;
NET "cntrl0_ddr1_cke" LOC = "V6" ;
NET "cntrl0_ddr1_clk0" LOC = "F4" ;
NET "cntrl0_ddr1_clk0b" LOC = "F3" ;
NET "cntrl0_ddr1_clk1" LOC = "E1" ;
NET "cntrl0_ddr1_clk1b" LOC = "E2" ;
NET "cntrl0_ddr1_clk2" LOC = "G7" ;
NET "cntrl0_ddr1_clk2b" LOC = "G6" ;
NET "cntrl0_ddr1_clk3" LOC = "E4" ;
NET "cntrl0_ddr1_clk3b" LOC = "E3" ;
NET "cntrl0_ddr1_csb" LOC = "U6" ;
NET "cntrl0_ddr1_dm(0)" LOC = "AB1" ;
NET "cntrl0_ddr1_dm(1)" LOC = "AA1" ;
NET "cntrl0_ddr1_dm(2)" LOC = "V7" ;
NET "cntrl0_ddr1_dm(3)" LOC = "T7" ;
NET "cntrl0_ddr1_dm(4)" LOC = "T5" ;
NET "cntrl0_ddr1_dm(5)" LOC = "R8" ;
NET "cntrl0_ddr1_dm(6)" LOC = "P7" ;
NET "cntrl0_ddr1_dm(7)" LOC = "L4" ;
NET "cntrl0_ddr1_rasb" LOC = "R6" ;
NET "cntrl0_ddr1_web" LOC = "L1" ;
INST "infrastructure_top0/clk_dcm0/DCM_INST1" LOC="DCM_X0Y0";
####################################################################################################
##### These timing constratint are for 133 MHz design. Please change it to required design frequency #######
###################################################################################################
NET "sys_clk_ibuf" TNM_NET = FFS(*) "SYS_CLK";
# TIMESPEC "TS_SYS_CLK" = PERIOD "SYS_CLK" 5 ns HIGH 50 %;
TIMESPEC "TS_SYS_CLK" = PERIOD "SYS_CLK" 6.0 ns HIGH 50 %;
NET "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div" MAXDELAY = 2000ps;
NET "*/ddr1_top0/iobs0/controller_iobs0/rst_dqs_div*" MAXDELAY = 2400ps;
NET "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delayed*" MAXDELAY = 2400ps;
NET "*/ddr1_top0/data_path0/data_read0/fifo*_wr_en" MAXDELAY = 1000ps;
#NET "*/ddr1_top0/data_path0/data_read0/fifo*_wr_en_1" MAXDELAY = 1050ps;
NET "*/ddr1_top0/data_path0/data_read0/fifo*_wr_addr(*)" MAXDELAY = 2050ps;
### NET "*/ddr1_top0/data_path0/data_read0/fifo*_wr_addr_1(*)" MAXDELAY = 2350ps;
NET "*/ddr1_top0/data_path0/data_read0/fifo*_rd_addr*" MAXDELAY = 3500ps;
NET "*/ddr1_top0/data_path0/data_read0/fifo*_rd_addr_r*" MAXDELAY = 3500ps;
NET "*/ddr1_top0/data_path0/data_read0/fifo*_data_out(*)" MAXDELAY = 3500ps;
NET "*/ddr1_top0/data_path0/user_output_data(*)" MAXDELAY = 3500ps;
NET "*/ddr1_top0/write_en_val*" MAXDELAY = 3500ps;
NET "*/ddr1_top0/reset90_r" TIG;
# NET "infrastructure_top0/cal_top0/cal_ctl0/tapForDqs(*)" TIG;
#INST "*/rst_calib*" TNM = "rst_calib";
#INST "*/u_dq" TNM = "u_dq";
# INST "*/infrastructure0/delay_sel_val1_r(*)" TNM = "delay_sel_val";
# INST "*/u_dq
#TIMESPEC TS06 = FROM "rst_calib" TO "u_dq" TIG;
#net "*/ddr1_top0/infrastructure_top0/lock_r2" TIG;
NET "infrastructure_top0/wait_200us" TNM = "wait200us";
NET "infrastructure_top0/wait_clk90" TNM = "wait200us90";
NET "infrastructure_top0/sys_rst*" TNM = "sysrst";
TIMESPEC TS01 = FROM "wait200us" TO "sysrst" TIG;
TIMESPEC TS02 = FROM "wait200us90" TO "sysrst" TIG;
TIMESPEC TS05 = FROM "wait200us" TO "wait200us90" TIG;
NET "*/ddr1_top0/controller0/rst_calib*" TIG;
INST "*/ddr1_top0/infrastructure0/delay_sel_val*" TIG;
INST "*/ddr1_top0/infrastructure0/rst_calib*" TIG;
INST "*/cal_top0/cal_ctl0/un1_tapForDqs*" TIG;
NET "reset_in" TIG;
NET "sys_rst*" TIG;
NET "*/controller0/rst0*" TIG;
NET "*/controller0/rst180*" TIG;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay*_col*" TIG;
INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delayed*" TIG;
######################################################################################
##### constraints to have the inverter connetion wire length to be the same ########
###### the following constraints are independent of frequency ######################
######################################################################################
###### maxdelay of 400 ps will not be met. This constraint is just to get a better delay####
NET "infrastructure_top0/cal_top0/tap_dly0/tap(7)" MAXDELAY = 400ps;
NET "infrastructure_top0/cal_top0/tap_dly0/tap(15)" MAXDELAY = 400ps;
NET "infrastructure_top0/cal_top0/tap_dly0/tap(23)" MAXDELAY = 400ps;
INST "*/ddr1_top0/controller0/rst_iob_out" IOB = TRUE;
##################################################################
##### constraints from the dqs pin ########
##################################################################
###### maxdelay of 460 ps will not be met. This constraint is just to get a better delay####
###### The reported delay will be in the range of 500 to 600 ps####
NET "*/ddr1_top0/dqs_int_delay_in*" MAXDELAY = 460ps;
###### maxdelay of 160 ps will not be met. This constraint is just to get a better delay####
###### The reported delay will be in the range of 200 to 360 ps####
NET "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay*_col*/delay*" MAXDELAY = 160ps;
###################################################################################################
######constraint to place flop1 and flop2 close togather for the calibration logic ###############
###################################################################################################
NET "infrastructure_top0/cal_top0/tap_dly0/flop1(*)" MAXDELAY = 3000ps;
##################################################################
########## Constraints for delay calibration logic#########
##################################################################
INST "infrastructure_top0/cal_top0/tap_dly0/l0" RLOC=X0Y6 ;
INST "infrastructure_top0/cal_top0/tap_dly0/l0" U_SET = "dr1_top0/infrastructure_top0/cal_top0/tap_dly0/l0" ;
INST "infrastructure_top0/cal_top0/tap_dly0/l1" RLOC=X0Y6;
INST "infrastructure_top0/cal_top0/tap_dly0/l1" U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
INST "infrastructure_top0/cal_top0/tap_dly0/l2" RLOC=X0Y7;
INST "infrastructure_top0/cal_top0/tap_dly0/l2" U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
INST "infrastructure_top0/cal_top0/tap_dly0/l3" RLOC=X0Y7;
INST "infrastructure_top0/cal_top0/tap_dly0/l3" U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
INST "infrastructure_top0/cal_top0/tap_dly0/l4" RLOC=X1Y6;
INST "infrastructure_top0/cal_top0/tap_dly0/l4" U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
INST "infrastructure_top0/cal_top0/tap_dly0/l5" RLOC=X1Y6;
INST "infrastructure_top0/cal_top0/tap_dly0/l5" U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
INST "infrastructure_top0/cal_top0/tap_dly0/l6" RLOC=X1Y7;
INST "infrastructure_top0/cal_top0/tap_dly0/l6" U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
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