mem_interface_top.ucf

XILINX memory interface generator. XILINX的外部存储器接口。

#############################################################
##  constraints for bit ddr1_dq, 37, location in tile: 1
NET "cntrl0_ddr1_dq(37)" LOC = N7;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit37" LOC = SLICE_X2Y72;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit37" LOC = SLICE_X2Y73;
#############################################################
##  constraints for bit ddr1_dq, 36, location in tile: 0
NET "cntrl0_ddr1_dq(36)" LOC = N8;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit36" LOC = SLICE_X0Y72;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit36" LOC = SLICE_X0Y73;
#############################################################
##  constraints for bit ddr1_dq, 39, location in tile: 1
NET "cntrl0_ddr1_dq(39)" LOC = M1;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit39" LOC = SLICE_X2Y74;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit39" LOC = SLICE_X2Y75;
#############################################################
##  constraints for bit ddr1_dq, 38, location in tile: 0
NET "cntrl0_ddr1_dq(38)" LOC = M2;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit38" LOC = SLICE_X0Y74;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit38" LOC = SLICE_X0Y75;
#############################################################
##  constraints for bit ddr1_dq, 41, location in tile: 1
NET "cntrl0_ddr1_dq(41)" LOC = M3;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit41" LOC = SLICE_X2Y76;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit41" LOC = SLICE_X2Y77;
#############################################################
##  constraints for bit ddr1_dq, 43, location in tile: 1
NET "cntrl0_ddr1_dq(43)" LOC = M6;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit43" LOC = SLICE_X2Y78;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit43" LOC = SLICE_X2Y79;
#############################################################
##  constraints for bit ddr1_dq, 40, location in tile: 0
NET "cntrl0_ddr1_dq(40)" LOC = M5;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit40" LOC = SLICE_X0Y78;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit40" LOC = SLICE_X0Y79;
#############################################################
##  constraints for bit ddr1_dq, 42, location in tile: 0
NET "cntrl0_ddr1_dq(42)" LOC = M8;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit42" LOC = SLICE_X0Y80;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit42" LOC = SLICE_X0Y81;
#############################################################
##  constraints for bit ddr1_dqs, 5, location in tile: 0
NET "cntrl0_ddr1_dqs(5)" LOC = L2;

## LUT location constraints for col 1
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay5_col0/one" LOC = SLICE_X2Y85;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay5_col0/one" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay5_col0/two" LOC = SLICE_X2Y84;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay5_col0/two" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay5_col0/three" LOC = SLICE_X3Y84;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay5_col0/three" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay5_col0/four" LOC = SLICE_X3Y85;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay5_col0/four" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay5_col0/five" LOC = SLICE_X2Y85;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay5_col0/five" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay5_col0/six" LOC = SLICE_X2Y84;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay5_col0/six" BEL = G;

## LUT location constraints for col 0
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay5_col1/one" LOC = SLICE_X0Y85;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay5_col1/one" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay5_col1/two" LOC = SLICE_X0Y84;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay5_col1/two" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay5_col1/three" LOC = SLICE_X1Y84;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay5_col1/three" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay5_col1/four" LOC = SLICE_X1Y85;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay5_col1/four" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay5_col1/five" LOC = SLICE_X0Y85;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay5_col1/five" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay5_col1/six" LOC = SLICE_X0Y84;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay5_col1/six" BEL = F;

########################WRITE ADD & WRITE_EN##########
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_50_wr_addr_inst/bit0" LOC = SLICE_X1Y80;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_50_wr_addr_inst/bit1" LOC = SLICE_X1Y80;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_50_wr_addr_inst/bit2" LOC = SLICE_X1Y81;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_50_wr_addr_inst/bit3" LOC = SLICE_X1Y81;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_51_wr_addr_inst/bit0" LOC = SLICE_X3Y80;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_51_wr_addr_inst/bit1" LOC = SLICE_X3Y80;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_51_wr_addr_inst/bit2" LOC = SLICE_X3Y81;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_51_wr_addr_inst/bit3" LOC = SLICE_X3Y81;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_50_wr_en_inst" LOC = SLICE_X1Y83;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_51_wr_en_inst" LOC = SLICE_X3Y83;

#############################################################
##  constraints for bit ddr1_dq, 45, location in tile: 1
NET "cntrl0_ddr1_dq(45)" LOC = L5;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit45" LOC = SLICE_X2Y86;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit45" LOC = SLICE_X2Y87;
#############################################################
##  constraints for bit ddr1_dq, 44, location in tile: 0
NET "cntrl0_ddr1_dq(44)" LOC = L6;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit44" LOC = SLICE_X0Y86;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit44" LOC = SLICE_X0Y87;
#############################################################
##  constraints for bit ddr1_dq, 47, location in tile: 1
NET "cntrl0_ddr1_dq(47)" LOC = L7;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit47" LOC = SLICE_X2Y88;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit47" LOC = SLICE_X2Y89;
#############################################################
##  constraints for bit ddr1_dq, 46, location in tile: 0
NET "cntrl0_ddr1_dq(46)" LOC = K2;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit46" LOC = SLICE_X0Y90;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit46" LOC = SLICE_X0Y91;
#############################################################
##  constraints for bit ddr1_dq, 49, location in tile: 1
NET "cntrl0_ddr1_dq(49)" LOC = K3;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit49" LOC = SLICE_X2Y92;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit49" LOC = SLICE_X2Y93;
#############################################################
##  constraints for bit ddr1_dq, 48, location in tile: 0
NET "cntrl0_ddr1_dq(48)" LOC = K4;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit48" LOC = SLICE_X0Y92;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit48" LOC = SLICE_X0Y93;
#############################################################
##  constraints for bit ddr1_dq, 51, location in tile: 1
NET "cntrl0_ddr1_dq(51)" LOC = K5;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit51" LOC = SLICE_X2Y94;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit51" LOC = SLICE_X2Y95;
#############################################################
##  constraints for bit ddr1_dq, 50, location in tile: 0
NET "cntrl0_ddr1_dq(50)" LOC = K6;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit50" LOC = SLICE_X0Y94;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit50" LOC = SLICE_X0Y95;
#############################################################
##  constraints for bit ddr1_dqs, 6, location in tile: 0
NET "cntrl0_ddr1_dqs(6)" LOC = J3;

## LUT location constraints for col 1
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay6_col0/one" LOC = SLICE_X2Y97;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay6_col0/one" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay6_col0/two" LOC = SLICE_X2Y96;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay6_col0/two" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay6_col0/three" LOC = SLICE_X3Y96;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay6_col0/three" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay6_col0/four" LOC = SLICE_X3Y97;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay6_col0/four" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay6_col0/five" LOC = SLICE_X2Y97;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay6_col0/five" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay6_col0/six" LOC = SLICE_X2Y96;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay6_col0/six" BEL = G;

## LUT location constraints for col 0
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay6_col1/one" LOC = SLICE_X0Y97;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay6_col1/one" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay6_col1/two" LOC = SLICE_X0Y96;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay6_col1/two" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay6_col1/three" LOC = SLICE_X1Y96;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay6_col1/three" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay6_col1/four" LOC = SLICE_X1Y97;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay6_col1/four" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay6_col1/five" LOC = SLICE_X0Y97;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay6_col1/five" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay6_col1/six" LOC = SLICE_X0Y96;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay6_col1/six" BEL = F;

########################WRITE ADD & WRITE_EN##########
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_60_wr_addr_inst/bit0" LOC = SLICE_X1Y92;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_60_wr_addr_inst/bit1" LOC = SLICE_X1Y92;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_60_wr_addr_inst/bit2" LOC = SLICE_X1Y93;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_60_wr_addr_inst/bit3" LOC = SLICE_X1Y93;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_61_wr_addr_inst/bit0" LOC = SLICE_X3Y92;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_61_wr_addr_inst/bit1" LOC = SLICE_X3Y92;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_61_wr_addr_inst/bit2" LOC = SLICE_X3Y93;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_61_wr_addr_inst/bit3" LOC = SLICE_X3Y93;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_60_wr_en_inst" LOC = SLICE_X1Y95;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_61_wr_en_inst" LOC = SLICE_X3Y95;

#############################################################
##  constraints for bit ddr1_dq, 53, location in tile: 1
NET "cntrl0_ddr1_dq(53)" LOC = J4;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit53" LOC = SLICE_X2Y98;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit53" LOC = SLICE_X2Y99;
#############################################################
##  constraints for bit ddr1_dq, 52, location in tile: 0
NET "cntrl0_ddr1_dq(52)" LOC = J5;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit52" LOC = SLICE_X0Y98;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit52" LOC = SLICE_X0Y99;
#############################################################
##  constraints for bit ddr1_dq, 55, location in tile: 1
NET "cntrl0_ddr1_dq(55)" LOC = K7;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit55" LOC = SLICE_X2Y100;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit55" LOC = SLICE_X2Y101;
#############################################################
##  constraints for bit ddr1_dq, 54, location in tile: 0
NET "cntrl0_ddr1_dq(54)" LOC = J7;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit54" LOC = SLICE_X0Y100;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit54" LOC = SLICE_X0Y101;
#############################################################
##  constraints for bit ddr1_