mem_interface_top.ucf

XILINX memory interface generator. XILINX的外部存储器接口。

 INST  "infrastructure_top0/cal_top0/tap_dly0/l26" RLOC=X0Y1;
 INST  "infrastructure_top0/cal_top0/tap_dly0/l26"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
 INST  "infrastructure_top0/cal_top0/tap_dly0/l27" RLOC=X0Y1;
 INST  "infrastructure_top0/cal_top0/tap_dly0/l27"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
 INST  "infrastructure_top0/cal_top0/tap_dly0/l28" RLOC=X1Y0;
 INST  "infrastructure_top0/cal_top0/tap_dly0/l28"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
 INST  "infrastructure_top0/cal_top0/tap_dly0/l29" RLOC=X1Y0;
 INST  "infrastructure_top0/cal_top0/tap_dly0/l29"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
 INST  "infrastructure_top0/cal_top0/tap_dly0/l30" RLOC=X1Y1;
 INST  "infrastructure_top0/cal_top0/tap_dly0/l30"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
 INST  "infrastructure_top0/cal_top0/tap_dly0/l31" RLOC=X1Y1;
 INST  "infrastructure_top0/cal_top0/tap_dly0/l31"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
 ##################################################################
 # Placement constraints for first stage flops in matched delay ckt
 ##################################################################

 INST  "infrastructure_top0/cal_top0/tap_dly0/r0"    RLOC=X0Y6;
 INST  "infrastructure_top0/cal_top0/tap_dly0/r0"   U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
 INST "infrastructure_top0/cal_top0/tap_dly0/r1" RLOC=X0Y6;
 INST  "infrastructure_top0/cal_top0/tap_dly0/r1"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
 INST "infrastructure_top0/cal_top0/tap_dly0/r2" RLOC=X0Y7;
 INST  "infrastructure_top0/cal_top0/tap_dly0/r2"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
 INST "infrastructure_top0/cal_top0/tap_dly0/r3" RLOC=X0Y7;
 INST  "infrastructure_top0/cal_top0/tap_dly0/r3"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
 INST "infrastructure_top0/cal_top0/tap_dly0/r4" RLOC=X1Y6;
 INST  "infrastructure_top0/cal_top0/tap_dly0/r4"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
 INST "infrastructure_top0/cal_top0/tap_dly0/r5" RLOC=X1Y6;
 INST  "infrastructure_top0/cal_top0/tap_dly0/r5"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
 INST "infrastructure_top0/cal_top0/tap_dly0/r6" RLOC=X1Y7;
 INST  "infrastructure_top0/cal_top0/tap_dly0/r6"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
 INST "infrastructure_top0/cal_top0/tap_dly0/r7" RLOC=X1Y7;
 INST  "infrastructure_top0/cal_top0/tap_dly0/r7"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
 INST "infrastructure_top0/cal_top0/tap_dly0/r8" RLOC=X0Y4;
 INST  "infrastructure_top0/cal_top0/tap_dly0/r8"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
 INST "infrastructure_top0/cal_top0/tap_dly0/r9" RLOC=X0Y4;
 INST  "infrastructure_top0/cal_top0/tap_dly0/r9"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
 INST "infrastructure_top0/cal_top0/tap_dly0/r10" RLOC=X0Y5;
 INST  "infrastructure_top0/cal_top0/tap_dly0/r10"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
 INST "infrastructure_top0/cal_top0/tap_dly0/r11" RLOC=X0Y5;
 INST  "infrastructure_top0/cal_top0/tap_dly0/r11"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
 INST "infrastructure_top0/cal_top0/tap_dly0/r12" RLOC=X1Y4;
 INST  "infrastructure_top0/cal_top0/tap_dly0/r12"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
 INST "infrastructure_top0/cal_top0/tap_dly0/r13" RLOC=X1Y4;
 INST  "infrastructure_top0/cal_top0/tap_dly0/r13"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
  INST "infrastructure_top0/cal_top0/tap_dly0/r14" RLOC=X1Y5;
  INST  "infrastructure_top0/cal_top0/tap_dly0/r14"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
  INST "infrastructure_top0/cal_top0/tap_dly0/r15" RLOC=X1Y5;
  INST  "infrastructure_top0/cal_top0/tap_dly0/r15"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
  INST  "infrastructure_top0/cal_top0/tap_dly0/r16" RLOC=X0Y2;
  INST  "infrastructure_top0/cal_top0/tap_dly0/r16"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
  INST  "infrastructure_top0/cal_top0/tap_dly0/r17" RLOC=X0Y2;
  INST  "infrastructure_top0/cal_top0/tap_dly0/r17"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
  INST  "infrastructure_top0/cal_top0/tap_dly0/r18" RLOC=X0Y3;
  INST  "infrastructure_top0/cal_top0/tap_dly0/r18"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
  INST  "infrastructure_top0/cal_top0/tap_dly0/r19" RLOC=X0Y3;
  INST  "infrastructure_top0/cal_top0/tap_dly0/r19"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
  INST  "infrastructure_top0/cal_top0/tap_dly0/r20" RLOC=X1Y2;
  INST  "infrastructure_top0/cal_top0/tap_dly0/r20"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
  INST  "infrastructure_top0/cal_top0/tap_dly0/r21" RLOC=X1Y2;
  INST  "infrastructure_top0/cal_top0/tap_dly0/r21"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
  INST  "infrastructure_top0/cal_top0/tap_dly0/r22" RLOC=X1Y3;
  INST  "infrastructure_top0/cal_top0/tap_dly0/r22"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
  INST  "infrastructure_top0/cal_top0/tap_dly0/r23" RLOC=X1Y3;
  INST  "infrastructure_top0/cal_top0/tap_dly0/r23"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
  INST  "infrastructure_top0/cal_top0/tap_dly0/r24" RLOC=X0Y0;
  INST  "infrastructure_top0/cal_top0/tap_dly0/r24"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
  INST  "infrastructure_top0/cal_top0/tap_dly0/r25" RLOC=X0Y0;
  INST  "infrastructure_top0/cal_top0/tap_dly0/r25"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
  INST  "infrastructure_top0/cal_top0/tap_dly0/r26" RLOC=X0Y1;
  INST  "infrastructure_top0/cal_top0/tap_dly0/r26"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
  INST  "infrastructure_top0/cal_top0/tap_dly0/r27" RLOC=X0Y1;
  INST  "infrastructure_top0/cal_top0/tap_dly0/r27"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
  INST  "infrastructure_top0/cal_top0/tap_dly0/r28" RLOC=X1Y0;
  INST  "infrastructure_top0/cal_top0/tap_dly0/r28"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
  INST  "infrastructure_top0/cal_top0/tap_dly0/r29" RLOC=X1Y0;
  INST  "infrastructure_top0/cal_top0/tap_dly0/r29"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
  INST  "infrastructure_top0/cal_top0/tap_dly0/r30" RLOC=X1Y1;
  INST  "infrastructure_top0/cal_top0/tap_dly0/r30"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
  INST  "infrastructure_top0/cal_top0/tap_dly0/r31" RLOC=X1Y1;
  INST  "infrastructure_top0/cal_top0/tap_dly0/r31"  U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
 ################################################################################################################
 ################################################################################################################
   INST "infrastructure_top0/cal_top0/tap_dly0/l0" BEL= G;
   INST "infrastructure_top0/cal_top0/tap_dly0/l1" BEL= F;
   INST "infrastructure_top0/cal_top0/tap_dly0/l2" BEL= G;
   INST "infrastructure_top0/cal_top0/tap_dly0/l3" BEL= F;
   INST "infrastructure_top0/cal_top0/tap_dly0/l4" BEL= G;
   INST "infrastructure_top0/cal_top0/tap_dly0/l5" BEL= F;
   INST "infrastructure_top0/cal_top0/tap_dly0/l6" BEL= G;
   INST "infrastructure_top0/cal_top0/tap_dly0/l7" BEL= F;
   INST "infrastructure_top0/cal_top0/tap_dly0/l8" BEL= G;
   INST "infrastructure_top0/cal_top0/tap_dly0/l9" BEL= F;
   INST "infrastructure_top0/cal_top0/tap_dly0/l10" BEL= G;
   INST "infrastructure_top0/cal_top0/tap_dly0/l11" BEL= F;
   INST "infrastructure_top0/cal_top0/tap_dly0/l12" BEL= G;
   INST "infrastructure_top0/cal_top0/tap_dly0/l13" BEL= F;
   INST "infrastructure_top0/cal_top0/tap_dly0/l14" BEL= G;
   INST "infrastructure_top0/cal_top0/tap_dly0/l15" BEL= F;
   INST "infrastructure_top0/cal_top0/tap_dly0/l16" BEL= G;
   INST "infrastructure_top0/cal_top0/tap_dly0/l17" BEL= F;
   INST "infrastructure_top0/cal_top0/tap_dly0/l18" BEL= G;
   INST "infrastructure_top0/cal_top0/tap_dly0/l19" BEL= F;
   INST "infrastructure_top0/cal_top0/tap_dly0/l20" BEL= G;
   INST "infrastructure_top0/cal_top0/tap_dly0/l21" BEL= F;
   INST "infrastructure_top0/cal_top0/tap_dly0/l22" BEL= G;
   INST "infrastructure_top0/cal_top0/tap_dly0/l23" BEL= F;
   INST "infrastructure_top0/cal_top0/tap_dly0/l24" BEL= G;
   INST "infrastructure_top0/cal_top0/tap_dly0/l25" BEL= F;
   INST "infrastructure_top0/cal_top0/tap_dly0/l26" BEL= G;
   INST "infrastructure_top0/cal_top0/tap_dly0/l27" BEL= F;
   INST "infrastructure_top0/cal_top0/tap_dly0/l28" BEL= G;
   INST "infrastructure_top0/cal_top0/tap_dly0/l29" BEL= F;
   INST "infrastructure_top0/cal_top0/tap_dly0/l30" BEL= G;
   INST "infrastructure_top0/cal_top0/tap_dly0/l31" BEL= F;
 #############################################################
 #############################################################
INST "infrastructure_top0/cal_top0/cal_ctl0" AREA_GROUP = cal_ctl;
INST "infrastructure_top0/cal_top0/tap_dly0" AREA_GROUP = cal_ctl;
######## Range for the delay calibration logic. ######;
########The range has to be changed for the device used.######;
AREA_GROUP "cal_ctl" RANGE = SLICE_X65Y85:SLICE_X74Y72;
AREA_GROUP "cal_ctl" GROUP = CLOSED;

 #NET "*/ddr1_top0/controller0/ddr_address*" IOB = TRUE;
 #NET "*/ddr1_top0/controller0/ddr_ba*" IOB = TRUE;

 INST "*/ddr1_top0/iobs0/controller_iobs0/iob_addr*" IOB = TRUE;
 INST "*/ddr1_top0/iobs0/controller_iobs0/iob_ba*" IOB = TRUE;

 INST "*/ddr1_top0/iobs0/controller_iobs0/iob_rasb" IOB = TRUE;
 INST "*/ddr1_top0/iobs0/controller_iobs0/iob_casb" IOB = TRUE;
 INST "*/ddr1_top0/iobs0/controller_iobs0/iob_web" IOB = TRUE;
 INST "*/ddr1_top0/iobs0/datapath_iobs0/ddr_dqs_iob*" IOB = TRUE;
 INST "*/ddr1_top0/iobs0/datapath_iobs0/ddr_dq_iob*" IOB = TRUE;
## INST "*/ddr1_top0/iobs0/datapath_iobs0/s3_dqs_iob*" IOB = TRUE; changed to make it equal for V2P ans Spartan3
## INST "*/ddr1_top0/iobs0/datapath_iobs0/s3_ddr_iob*" IOB = TRUE;
#############################################################
##  constraints for bit ddr1_dq, 1, location in tile: 1
NET "cntrl0_ddr1_dq(1)" LOC = AB4;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit1" LOC = SLICE_X2Y2;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit1" LOC = SLICE_X2Y3;
#############################################################
##  constraints for bit ddr1_dq, 0, location in tile: 0
NET "cntrl0_ddr1_dq(0)" LOC = AB3;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit0" LOC = SLICE_X0Y2;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit0" LOC = SLICE_X0Y3;
#############################################################
##  constraints for bit ddr1_dq, 2, location in tile: 0
NET "cntrl0_ddr1_dq(2)" LOC = AC1;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit2" LOC = SLICE_X0Y4;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit2" LOC = SLICE_X0Y5;
#############################################################
##  constraints for bit ddr1_dq, 3, location in tile: 1
NET "cntrl0_ddr1_dq(3)" LOC = AB2;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit3" LOC = SLICE_X2Y6;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit3" LOC = SLICE_X2Y7;
#############################################################
##  constraints for bit ddr1_dqs, 0, location in tile: 0
NET "cntrl0_ddr1_dqs(0)" LOC = Y6;

## LUT location constraints for col 1
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/one" LOC = SLICE_X2Y9;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/one" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/two" LOC = SLICE_X2Y8;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/two" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/three" LOC = SLICE_X3Y8;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/three" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/four" LOC = SLICE_X3Y9;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/four" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/five" LOC = SLICE_X2Y9;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/five" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/six" LOC = SLICE_X2Y8;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/six" BEL = G;

## LUT location constraints for col 0
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/one" LOC = SLICE_X0Y9;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/one" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/two" LOC = SLICE_X0Y8;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/two" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/three" LOC = SLICE_X1Y8;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/three" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/four" LOC = SLICE_X1Y9;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/four" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/five" LOC = SLICE_X0Y9;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/five" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/six" LOC = SLICE_X0Y8;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/six" BEL = F;

########################WRITE ADD & WRITE_EN##########
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_00_wr_addr_inst/bit0" LOC = SLICE_X1Y4;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_00_wr_addr_inst/bit1" LOC = SLICE_X1Y4;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_00_wr_addr_inst/bit2" LOC = SLICE_X1Y5;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_00_wr_addr_inst/bit3" LOC = SLICE_X1Y5;