mem_interface_top.ucf

XILINX memory interface generator. XILINX的外部存储器接口。

INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col0/six" BEL = G;

## LUT location constraints for col 0
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col1/one" LOC = SLICE_X0Y33;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col1/one" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col1/two" LOC = SLICE_X0Y32;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col1/two" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col1/three" LOC = SLICE_X1Y32;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col1/three" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col1/four" LOC = SLICE_X1Y33;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col1/four" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col1/five" LOC = SLICE_X0Y33;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col1/five" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col1/six" LOC = SLICE_X0Y32;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col1/six" BEL = F;

########################WRITE ADD & WRITE_EN##########
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_20_wr_addr_inst/bit0" LOC = SLICE_X1Y28;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_20_wr_addr_inst/bit1" LOC = SLICE_X1Y28;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_20_wr_addr_inst/bit2" LOC = SLICE_X1Y29;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_20_wr_addr_inst/bit3" LOC = SLICE_X1Y29;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_21_wr_addr_inst/bit0" LOC = SLICE_X3Y28;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_21_wr_addr_inst/bit1" LOC = SLICE_X3Y28;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_21_wr_addr_inst/bit2" LOC = SLICE_X3Y29;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_21_wr_addr_inst/bit3" LOC = SLICE_X3Y29;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_20_wr_en_inst" LOC = SLICE_X1Y31;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_21_wr_en_inst" LOC = SLICE_X3Y31;

#############################################################
##  constraints for bit ddr1_dq, 20, location in tile: 0
NET "cntrl0_ddr1_dq(20)" LOC = U3;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit20" LOC = SLICE_X0Y34;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit20" LOC = SLICE_X0Y35;
#############################################################
##  constraints for bit ddr1_dq, 21, location in tile: 1
NET "cntrl0_ddr1_dq(21)" LOC = U2;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit21" LOC = SLICE_X2Y36;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit21" LOC = SLICE_X2Y37;
#############################################################
##  constraints for bit ddr1_dq, 22, location in tile: 0
NET "cntrl0_ddr1_dq(22)" LOC = U1;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit22" LOC = SLICE_X0Y36;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit22" LOC = SLICE_X0Y37;
#############################################################
##  constraints for bit ddr1_dq, 23, location in tile: 1
NET "cntrl0_ddr1_dq(23)" LOC = T8;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit23" LOC = SLICE_X2Y38;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit23" LOC = SLICE_X2Y39;
#############################################################
##  constraints for bit ddr1_dq, 25, location in tile: 1
NET "cntrl0_ddr1_dq(25)" LOC = T6;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit25" LOC = SLICE_X2Y40;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit25" LOC = SLICE_X2Y41;
#############################################################
##  constraints for bit ddr1_dq, 27, location in tile: 1
NET "cntrl0_ddr1_dq(27)" LOC = T2;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit27" LOC = SLICE_X2Y42;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit27" LOC = SLICE_X2Y43;
#############################################################
##  constraints for bit ddr1_dq, 24, location in tile: 0
NET "cntrl0_ddr1_dq(24)" LOC = T1;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit24" LOC = SLICE_X0Y42;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit24" LOC = SLICE_X0Y43;
#############################################################
##  constraints for bit ddr1_dq, 26, location in tile: 0
NET "cntrl0_ddr1_dq(26)" LOC = R7;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit26" LOC = SLICE_X0Y46;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit26" LOC = SLICE_X0Y47;
#############################################################
##  constraints for bit ddr1_dqs, 3, location in tile: 0
NET "cntrl0_ddr1_dqs(3)" LOC = R5;

## LUT location constraints for col 1
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col0/one" LOC = SLICE_X2Y49;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col0/one" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col0/two" LOC = SLICE_X2Y48;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col0/two" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col0/three" LOC = SLICE_X3Y48;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col0/three" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col0/four" LOC = SLICE_X3Y49;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col0/four" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col0/five" LOC = SLICE_X2Y49;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col0/five" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col0/six" LOC = SLICE_X2Y48;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col0/six" BEL = G;

## LUT location constraints for col 0
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col1/one" LOC = SLICE_X0Y49;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col1/one" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col1/two" LOC = SLICE_X0Y48;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col1/two" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col1/three" LOC = SLICE_X1Y48;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col1/three" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col1/four" LOC = SLICE_X1Y49;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col1/four" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col1/five" LOC = SLICE_X0Y49;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col1/five" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col1/six" LOC = SLICE_X0Y48;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col1/six" BEL = F;

########################WRITE ADD & WRITE_EN##########
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_30_wr_addr_inst/bit0" LOC = SLICE_X1Y44;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_30_wr_addr_inst/bit1" LOC = SLICE_X1Y44;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_30_wr_addr_inst/bit2" LOC = SLICE_X1Y45;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_30_wr_addr_inst/bit3" LOC = SLICE_X1Y45;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_31_wr_addr_inst/bit0" LOC = SLICE_X3Y44;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_31_wr_addr_inst/bit1" LOC = SLICE_X3Y44;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_31_wr_addr_inst/bit2" LOC = SLICE_X3Y45;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_31_wr_addr_inst/bit3" LOC = SLICE_X3Y45;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_30_wr_en_inst" LOC = SLICE_X1Y47;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_31_wr_en_inst" LOC = SLICE_X3Y47;

#############################################################
##  constraints for bit ddr1_dq, 29, location in tile: 1
NET "cntrl0_ddr1_dq(29)" LOC = T4;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit29" LOC = SLICE_X2Y50;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit29" LOC = SLICE_X2Y51;
#############################################################
##  constraints for bit ddr1_dq, 28, location in tile: 0
NET "cntrl0_ddr1_dq(28)" LOC = R3;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit28" LOC = SLICE_X0Y50;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit28" LOC = SLICE_X0Y51;
#############################################################
##  constraints for bit ddr1_dq, 30, location in tile: 0
NET "cntrl0_ddr1_dq(30)" LOC = R1;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit30" LOC = SLICE_X0Y52;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit30" LOC = SLICE_X0Y53;
#############################################################
##  constraints for bit ddr1_dq, 31, location in tile: 1
NET "cntrl0_ddr1_dq(31)" LOC = P8;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit31" LOC = SLICE_X2Y54;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit31" LOC = SLICE_X2Y55;
#############################################################
##  constraints for bit rst_dqs_div_in, 1, location in tile: 1
NET "cntrl0_rst_dqs_div_in" LOC = P4; 

## LUT location constraints for col 1
INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delayed1/one" LOC = SLICE_X2Y61;
INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delayed1/one" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delayed1/two" LOC = SLICE_X2Y60;
INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delayed1/two" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delayed1/three" LOC = SLICE_X3Y60;
INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delayed1/three" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delayed1/four" LOC = SLICE_X3Y61;
INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delayed1/four" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delayed1/five" LOC = SLICE_X2Y61;
INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delayed1/five" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delayed1/six" LOC = SLICE_X2Y60;
INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delayed1/six" BEL = G;

## LUT location constraints for col 0
#INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delayed2/one" LOC = SLICE_X0Y61;
#INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delayed2/one" BEL = F;
#INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delayed2/two" LOC = SLICE_X0Y60;
#INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delayed2/two" BEL = G;
#INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delayed2/three" LOC = SLICE_X1Y60;
#INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delayed2/three" BEL = G;
#INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delayed2/four" LOC = SLICE_X1Y61;
#INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delayed2/four" BEL = G;
#INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delayed2/five" LOC = SLICE_X0Y61;
#INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delayed2/five" BEL = G;
#INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delayed2/six" LOC = SLICE_X0Y60;
#INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delayed2/six" BEL = F;
#############################################################
##  constraints for bit rst_dqs_div_out, 1, location in tile: 0
NET "cntrl0_rst_dqs_div_out" LOC = P3;
#############################################################
##  constraints for bit ddr1_dq, 33, location in tile: 1
NET "cntrl0_ddr1_dq(33)" LOC = P2;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit33" LOC = SLICE_X2Y62;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit33" LOC = SLICE_X2Y63;
#############################################################
##  constraints for bit ddr1_dq, 32, location in tile: 0
NET "cntrl0_ddr1_dq(32)" LOC = N2;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit32" LOC = SLICE_X0Y64;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit32" LOC = SLICE_X0Y65;
#############################################################
##  constraints for bit ddr1_dq, 35, location in tile: 1
NET "cntrl0_ddr1_dq(35)" LOC = N3;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit35" LOC = SLICE_X2Y66;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit35" LOC = SLICE_X2Y67;
#############################################################
##  constraints for bit ddr1_dq, 34, location in tile: 0
NET "cntrl0_ddr1_dq(34)" LOC = N4;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit34" LOC = SLICE_X0Y66;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit34" LOC = SLICE_X0Y67;
#############################################################
##  constraints for bit ddr1_dqs, 4, location in tile: 0
NET "cntrl0_ddr1_dqs(4)" LOC = N6;

## LUT location constraints for col 1
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay4_col0/one" LOC = SLICE_X2Y69;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay4_col0/one" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay4_col0/two" LOC = SLICE_X2Y68;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay4_col0/two" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay4_col0/three" LOC = SLICE_X3Y68;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay4_col0/three" BEL = G;