mem_interface_top.ucf

XILINX memory interface generator. XILINX的外部存储器接口。

NET "cntrl0_ddr1_dq(3)" LOC = AB2;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit3" LOC = SLICE_X2Y6;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit3" LOC = SLICE_X2Y7;
#############################################################
##  constraints for bit ddr1_dqs, 0, location in tile: 0
NET "cntrl0_ddr1_dqs(0)" LOC = Y6;

## LUT location constraints for col 1
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/one" LOC = SLICE_X2Y9;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/one" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/two" LOC = SLICE_X2Y8;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/two" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/three" LOC = SLICE_X3Y8;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/three" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/four" LOC = SLICE_X3Y9;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/four" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/five" LOC = SLICE_X2Y9;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/five" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/six" LOC = SLICE_X2Y8;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/six" BEL = G;

## LUT location constraints for col 0
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/one" LOC = SLICE_X0Y9;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/one" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/two" LOC = SLICE_X0Y8;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/two" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/three" LOC = SLICE_X1Y8;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/three" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/four" LOC = SLICE_X1Y9;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/four" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/five" LOC = SLICE_X0Y9;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/five" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/six" LOC = SLICE_X0Y8;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/six" BEL = F;

########################WRITE ADD & WRITE_EN##########
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_00_wr_addr_inst/bit0" LOC = SLICE_X1Y4;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_00_wr_addr_inst/bit1" LOC = SLICE_X1Y4;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_00_wr_addr_inst/bit2" LOC = SLICE_X1Y5;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_00_wr_addr_inst/bit3" LOC = SLICE_X1Y5;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_01_wr_addr_inst/bit0" LOC = SLICE_X3Y4;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_01_wr_addr_inst/bit1" LOC = SLICE_X3Y4;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_01_wr_addr_inst/bit2" LOC = SLICE_X3Y5;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_01_wr_addr_inst/bit3" LOC = SLICE_X3Y5;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_00_wr_en_inst" LOC = SLICE_X1Y7;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_01_wr_en_inst" LOC = SLICE_X3Y7;

#INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_00_wr_addr_inst_1/bit0" LOC = SLICE_X3Y12;
#INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_00_wr_addr_inst_1/bit1" LOC = SLICE_X3Y12;
#INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_00_wr_addr_inst_1/bit2" LOC = SLICE_X3Y13;
#INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_00_wr_addr_inst_1/bit3" LOC = SLICE_X3Y13;
#INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_01_wr_addr_inst_1/bit0" LOC = SLICE_X1Y12;
#INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_01_wr_addr_inst_1/bit1" LOC = SLICE_X1Y12;
#INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_01_wr_addr_inst_1/bit2" LOC = SLICE_X1Y13;
#INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_01_wr_addr_inst_1/bit3" LOC = SLICE_X1Y13;
#INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_00_wr_en_inst_1" LOC = SLICE_X3Y11;
#INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_01_wr_en_inst_1" LOC = SLICE_X1Y11;
#############################################################
##  constraints for bit ddr1_dq, 5, location in tile: 1
NET "cntrl0_ddr1_dq(5)" LOC = AA4;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit5" LOC = SLICE_X2Y10;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit5" LOC = SLICE_X2Y11;
#############################################################
##  constraints for bit ddr1_dq, 4, location in tile: 0
NET "cntrl0_ddr1_dq(4)" LOC = AA3;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit4" LOC = SLICE_X0Y10;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit4" LOC = SLICE_X0Y11;
#############################################################
##  constraints for bit ddr1_dq, 7, location in tile: 1
NET "cntrl0_ddr1_dq(7)" LOC = Y5;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit7" LOC = SLICE_X2Y12;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit7" LOC = SLICE_X2Y13;
#############################################################
##  constraints for bit ddr1_dq, 6, location in tile: 0
NET "cntrl0_ddr1_dq(6)" LOC = Y4;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit6" LOC = SLICE_X0Y12;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit6" LOC = SLICE_X0Y13;
#############################################################
##  constraints for bit ddr1_dq, 9, location in tile: 1
NET "cntrl0_ddr1_dq(9)" LOC = Y2;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit9" LOC = SLICE_X2Y16;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit9" LOC = SLICE_X2Y17;
#############################################################
##  constraints for bit ddr1_dq, 8, location in tile: 0
NET "cntrl0_ddr1_dq(8)" LOC = Y1;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit8" LOC = SLICE_X0Y16;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit8" LOC = SLICE_X0Y17;
#############################################################
##  constraints for bit ddr1_dq, 11, location in tile: 1
NET "cntrl0_ddr1_dq(11)" LOC = W7;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit11" LOC = SLICE_X2Y18;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit11" LOC = SLICE_X2Y19;
#############################################################
##  constraints for bit ddr1_dq, 10, location in tile: 0
NET "cntrl0_ddr1_dq(10)" LOC = W6;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit10" LOC = SLICE_X0Y18;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit10" LOC = SLICE_X0Y19;
#############################################################
##  constraints for bit ddr1_dqs, 1, location in tile: 0
NET "cntrl0_ddr1_dqs(1)" LOC = W5;

## LUT location constraints for col 1
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col0/one" LOC = SLICE_X2Y21;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col0/one" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col0/two" LOC = SLICE_X2Y20;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col0/two" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col0/three" LOC = SLICE_X3Y20;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col0/three" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col0/four" LOC = SLICE_X3Y21;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col0/four" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col0/five" LOC = SLICE_X2Y21;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col0/five" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col0/six" LOC = SLICE_X2Y20;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col0/six" BEL = G;

## LUT location constraints for col 0
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col1/one" LOC = SLICE_X0Y21;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col1/one" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col1/two" LOC = SLICE_X0Y20;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col1/two" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col1/three" LOC = SLICE_X1Y20;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col1/three" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col1/four" LOC = SLICE_X1Y21;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col1/four" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col1/five" LOC = SLICE_X0Y21;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col1/five" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col1/six" LOC = SLICE_X0Y20;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col1/six" BEL = F;

########################WRITE ADD & WRITE_EN##########
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_10_wr_addr_inst/bit0" LOC = SLICE_X1Y16;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_10_wr_addr_inst/bit1" LOC = SLICE_X1Y16;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_10_wr_addr_inst/bit2" LOC = SLICE_X1Y17;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_10_wr_addr_inst/bit3" LOC = SLICE_X1Y17;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_11_wr_addr_inst/bit0" LOC = SLICE_X3Y16;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_11_wr_addr_inst/bit1" LOC = SLICE_X3Y16;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_11_wr_addr_inst/bit2" LOC = SLICE_X3Y17;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_11_wr_addr_inst/bit3" LOC = SLICE_X3Y17;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_10_wr_en_inst" LOC = SLICE_X1Y19;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_11_wr_en_inst" LOC = SLICE_X3Y19;

#############################################################
##  constraints for bit ddr1_dq, 13, location in tile: 1
NET "cntrl0_ddr1_dq(13)" LOC = W4;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit13" LOC = SLICE_X2Y22;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit13" LOC = SLICE_X2Y23;
#############################################################
##  constraints for bit ddr1_dq, 15, location in tile: 1
NET "cntrl0_ddr1_dq(15)" LOC = W2;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit15" LOC = SLICE_X2Y24;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit15" LOC = SLICE_X2Y25;
#############################################################
##  constraints for bit ddr1_dq, 12, location in tile: 0
NET "cntrl0_ddr1_dq(12)" LOC = W1;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit12" LOC = SLICE_X0Y24;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit12" LOC = SLICE_X0Y25;
#############################################################
##  constraints for bit ddr1_dq, 14, location in tile: 0
NET "cntrl0_ddr1_dq(14)" LOC = U7;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit14" LOC = SLICE_X0Y26;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit14" LOC = SLICE_X0Y27;
#############################################################
##  constraints for bit ddr1_dq, 17, location in tile: 1
NET "cntrl0_ddr1_dq(17)" LOC = V5;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit17" LOC = SLICE_X2Y28;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit17" LOC = SLICE_X2Y29;
#############################################################
##  constraints for bit ddr1_dq, 16, location in tile: 0
NET "cntrl0_ddr1_dq(16)" LOC = V4;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit16" LOC = SLICE_X0Y28;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit16" LOC = SLICE_X0Y29;
#############################################################
##  constraints for bit ddr1_dq, 19, location in tile: 1
NET "cntrl0_ddr1_dq(19)" LOC = V3;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit19" LOC = SLICE_X2Y30;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit19" LOC = SLICE_X2Y31;
#############################################################
##  constraints for bit ddr1_dq, 18, location in tile: 0
NET "cntrl0_ddr1_dq(18)" LOC = V2;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit18" LOC = SLICE_X0Y30;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit18" LOC = SLICE_X0Y31;
#############################################################
##  constraints for bit ddr1_dqs, 2, location in tile: 0
NET "cntrl0_ddr1_dqs(2)" LOC = U5;

## LUT location constraints for col 1
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col0/one" LOC = SLICE_X2Y33;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col0/one" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col0/two" LOC = SLICE_X2Y32;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col0/two" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col0/three" LOC = SLICE_X3Y32;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col0/three" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col0/four" LOC = SLICE_X3Y33;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col0/four" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col0/five" LOC = SLICE_X2Y33;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col0/five" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col0/six" LOC = SLICE_X2Y32;