dcmx5y0_2vp100.edn

XILINX memory interface generator. XILINX的外部存储器接口。

(edif dcmx5y0_2vp100
  (edifVersion 2 0 0)
  (edifLevel 0)
  (keywordMap (keywordLevel 0))
  (status
    (written
      (timeStamp 2004 2 18 14 1 24)
      (author "Synplicity, Inc.")
      (program "Synplify" (version "7.3.3, Build 024R"))
     )
   )
  (library VIRTEX
    (edifLevel 0)
    (technology (numberDefinition ))
    (cell LUT4_L (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I0 (direction INPUT))
           (port I1 (direction INPUT))
           (port I2 (direction INPUT))
           (port I3 (direction INPUT))
           (port LO (direction OUTPUT))
         )
       )
    )
    (cell LUT4 (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I0 (direction INPUT))
           (port I1 (direction INPUT))
           (port I2 (direction INPUT))
           (port I3 (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
  )
  (library UNILIB
    (edifLevel 0)
    (technology (numberDefinition ))
    (cell VCC (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port P (direction OUTPUT))
         )
       )
    )
  )
  (library work
    (edifLevel 0)
    (technology (numberDefinition ))
    (cell dcmx5y0_2vp100 (cellType GENERIC)
       (view structure (viewType NETLIST)
         (interface
           (port clock1_in (direction INPUT)
 )
           (port clock2_in (direction INPUT)
 )
           (port clock1_out (direction OUTPUT))
           (port clock2_out (direction OUTPUT))
         )
         (contents
          (instance VCC (viewRef PRIM (cellRef VCC (libraryRef UNILIB)))          )
          (instance BUF1_1 (viewRef PRIM (cellRef LUT4 (libraryRef VIRTEX)))
           (property lock_pins (string ""))
           (property bel (string "G"))
           (property loc (string "SLICE_X183Y1"))
           (property init (string "f0f0"))
          )
          (instance INV1_1 (viewRef PRIM (cellRef LUT4 (libraryRef VIRTEX)))
           (property lock_pins (string ""))
           (property bel (string "F"))
           (property loc (string "SLICE_X165Y1"))
           (property init (string "3333"))
          )
          (instance INV2_1 (viewRef PRIM (cellRef LUT4 (libraryRef VIRTEX)))
           (property lock_pins (string ""))
           (property bel (string "F"))
           (property loc (string "SLICE_X94Y0"))
           (property init (string "3333"))
          )
          (instance BUF2_1 (viewRef PRIM (cellRef LUT4 (libraryRef VIRTEX)))
           (property lock_pins (string ""))
           (property bel (string "G"))
           (property loc (string "SLICE_X94Y0"))
           (property init (string "aaaa"))
          )
          (instance BUF1_2 (viewRef PRIM (cellRef LUT4 (libraryRef VIRTEX)))
           (property lock_pins (string ""))
           (property bel (string "G"))
           (property loc (string "SLICE_X182Y0"))
           (property init (string "ff00"))
          )
          (instance INV1_2 (viewRef PRIM (cellRef LUT4 (libraryRef VIRTEX)))
           (property lock_pins (string ""))
           (property bel (string "F"))
           (property loc (string "SLICE_X164Y0"))
           (property init (string "3333"))
          )
          (instance INV2_2 (viewRef PRIM (cellRef LUT4 (libraryRef VIRTEX)))
           (property lock_pins (string ""))
           (property bel (string "G"))
           (property loc (string "SLICE_X95Y1"))
           (property init (string "3333"))
          )
          (instance BUF2_2 (viewRef PRIM (cellRef LUT4_L (libraryRef VIRTEX)))
           (property lock_pins (string ""))
           (property bel (string "F"))
           (property loc (string "SLICE_X95Y1"))
           (property init (string "ff00"))
          )
          (net clock1_in (joined
           (portRef clock1_in)
           (portRef I2 (instanceRef BUF1_1))
          ))
          (net clock2_in (joined
           (portRef clock2_in)
           (portRef I3 (instanceRef BUF1_2))
          ))
          (net clock1_out (joined
           (portRef clock1_out)
           (portRef O (instanceRef BUF2_1))
           )
          )
          (net clock2_out (joined
           (portRef clock2_out)
           (portRef LO (instanceRef BUF2_2))
           )
          )
          (net clkd1buf_1 (joined
           (portRef I1 (instanceRef INV1_1))
           (portRef O (instanceRef BUF1_1))
           )
           (property route (string "{2;1;-5!-1;193872;202480;14;276;480;33;13!0;-11688;-801;42!1;-14632;258;2!2;-6912;0!3;-2368;684;0!4;120;-365;4;249;480;11!}"))
          )
          (net clkd1inv_1 (joined
           (portRef I1 (instanceRef INV2_1))
           (portRef O (instanceRef INV1_1))
           )
           (property route (string "{2;1;-5!-1;158552;-202232;14;249;7;30;13!0;-12536;-1663;42!1;-20968;-194!2;-21656;0!3;-21656;0!4;-21424;194!5;-21656;0!6;-14072;22;2!7;-7688;86!8;-7056;-86!9;1216;782;0!10;120;-365;4;144;4;11!}"))
          )
          (net clkd2buf_1 (joined
           (portRef I0 (instanceRef BUF2_1))
           (portRef O (instanceRef INV2_1))
           )
          )
          (net clkd1buf_2 (joined
           (portRef I1 (instanceRef INV1_2))
           (portRef O (instanceRef BUF1_2))
           )
           (property route (string "{2;1;-5!-1;194032;203512;14;276;483;33;13!0;-11848;631;42!1;-14584;-234;2!2;-6912;0!3;-2463;-621;0!4;327;0;4;249;483;11!}"))
          )
          (net clkd1inv_2 (joined
           (portRef I1 (instanceRef INV2_2))
           (portRef O (instanceRef INV1_2))
           )
           (property route (string "{2;1;-5!-1;158392;-203264;14;249;4;30;13!0;-12360;1573;42!1;-20984;178!2;-21656;0!3;-21656;0!4;-21408;-178!5;-21656;0!6;-14088;-22;2!7;-7672;-78!8;-7072;78!9;1169;-631;0!10;327;0;4;144;7;19!}"))
          )
          (net (rename VCCZ0 "VCC") (joined
           (portRef P (instanceRef VCC))
           (portRef I2 (instanceRef BUF2_2))
           (portRef I1 (instanceRef BUF2_2))
           (portRef I0 (instanceRef BUF2_2))
           (portRef I3 (instanceRef INV2_2))
           (portRef I2 (instanceRef INV2_2))
           (portRef I0 (instanceRef INV2_2))
           (portRef I3 (instanceRef INV1_2))
           (portRef I2 (instanceRef INV1_2))
           (portRef I0 (instanceRef INV1_2))
           (portRef I2 (instanceRef BUF1_2))
           (portRef I1 (instanceRef BUF1_2))
           (portRef I0 (instanceRef BUF1_2))
           (portRef I3 (instanceRef BUF2_1))
           (portRef I2 (instanceRef BUF2_1))
           (portRef I1 (instanceRef BUF2_1))
           (portRef I3 (instanceRef INV2_1))
           (portRef I2 (instanceRef INV2_1))
           (portRef I0 (instanceRef INV2_1))
           (portRef I3 (instanceRef INV1_1))
           (portRef I2 (instanceRef INV1_1))
           (portRef I0 (instanceRef INV1_1))
           (portRef I3 (instanceRef BUF1_1))
           (portRef I1 (instanceRef BUF1_1))
           (portRef I0 (instanceRef BUF1_1))
          ))
          (net clkd2inv_2 (joined
           (portRef O (instanceRef INV2_2))
           (portRef I3 (instanceRef BUF2_2))
          ))
         )
        (property KEEP_HIERARCHY (string "TRUE"))
       )
    )
  )
  (design dcmx5y0_2vp100 (cellRef dcmx5y0_2vp100 (libraryRef work))
	(property PART (string "xc2vp100ff1704-5") (owner "Xilinx")))
)