2vp100ff1696.txt

XILINX memory interface generator. XILINX的外部存储器接口。

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# Calibration Circuit Constraints
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INST "%sinfrastructure_top0/cal_top0/cal_dcm" LOC="DCM_X4Y0"; 

NET "%sinfrastructure_top0/cal_top0/ckt_to_cal/delay1" KEEP;
NET "%sinfrastructure_top0/cal_top0/ckt_to_cal/delay2" KEEP;
NET "%sinfrastructure_top0/cal_top0/ckt_to_cal/delay3" KEEP;
NET "%sinfrastructure_top0/cal_top0/ckt_to_cal/delay4" KEEP;
NET "%sinfrastructure_top0/cal_top0/ckt_to_cal/delay5" KEEP;

NET "%sinfrastructure_top0/cal_top0/cal_ctl0/selTap(4)" S;

INST "%sinfrastructure_top0/cal_top0" AREA_GROUP=gp1;
AREA_GROUP "gp1" RANGE = SLICE_X136Y0:SLICE_X159Y15;

INST "%sinfrastructure_top0/cal_top0/cal_clkd2" LOC = SLICE_X156Y0;
INST "%sinfrastructure_top0/cal_top0/cal_phClkd2" LOC = SLICE_X156Y3;

INST "%sinfrastructure_top0/cal_top0/hxSampReg0" LOC = SLICE_X158Y0;

NET "%sinfrastructure_top0/cal_top0/clkDiv2" MAXDELAY = 600 ps;
NET "%sinfrastructure_top0/cal_top0/phClkDiv2" MAXDELAY = 600 ps;

INST "%sinfrastructure_top0/cal_top0/cal_suClkd2" LOC = SLICE_X156Y4;
INST "%sinfrastructure_top0/cal_top0/cal_suPhClkd2" LOC = SLICE_X158Y5;
INST "%sinfrastructure_top0/cal_top0/phSampReg0" LOC = SLICE_X158Y4;

NET "%sinfrastructure_top0/cal_top0/suClkDiv2" MAXDELAY = 600ps;
NET "%sinfrastructure_top0/cal_top0/suPhClkDiv2" MAXDELAY = 700ps;
#############################################################
# LUT Location Constraints for dqs_delay Circuit
#############################################################
 INST "%sinfrastructure_top0/cal_top0/ckt_to_cal/one" LOC = SLICE_X158Y2; 
 INST "%sinfrastructure_top0/cal_top0/ckt_to_cal/one" BEL = F; 
 INST "%sinfrastructure_top0/cal_top0/ckt_to_cal/two" LOC = SLICE_X158Y3; 
 INST "%sinfrastructure_top0/cal_top0/ckt_to_cal/two" BEL = F; 
 INST "%sinfrastructure_top0/cal_top0/ckt_to_cal/three" LOC = SLICE_X158Y3; 
 INST "%sinfrastructure_top0/cal_top0/ckt_to_cal/three" BEL = G; 
 INST "%sinfrastructure_top0/cal_top0/ckt_to_cal/four" LOC = SLICE_X159Y2; 
 INST "%sinfrastructure_top0/cal_top0/ckt_to_cal/four" BEL = F; 
 INST "%sinfrastructure_top0/cal_top0/ckt_to_cal/five" LOC = SLICE_X159Y2; 
 INST "%sinfrastructure_top0/cal_top0/ckt_to_cal/five" BEL = G; 
 INST "%sinfrastructure_top0/cal_top0/ckt_to_cal/six" LOC = SLICE_X159Y3; 
 INST "%sinfrastructure_top0/cal_top0/ckt_to_cal/six" BEL = G; 


###no_dcm
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# DCM, MACRO and BUFG  Constraints

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INST "%sinfrastructure_top0/clk_dcm0/DCM_INST1" LOC="DCM_X5Y0"; 

INST "%sinfrastructure_top0/clk_dcm0/BUFG_CLK0/u1" LOC="BUFGMUX6P";
INST "%sinfrastructure_top0/clk_dcm0/BUFG_CLK90/u1" LOC="BUFGMUX7S";

NET "%sinfrastructure_top0/clk_dcm0/clk0dcm" MAXDELAY = 0.450ns;
NET "%sinfrastructure_top0/clk_dcm0/clk90dcm" MAXDELAY = 0.450ns;
NET "%sinfrastructure_top0/clk_dcm0/clk0d2inv" MAXDELAY = 0.755ns;
NET "%sinfrastructure_top0/clk_dcm0/clk90d2inv" MAXDELAY = 0.755ns;


##############################################################################
# MaxDelay constraints                                                                                                #
##############################################################################

NET "%sinfrastructure_top0/clk_dcm0/clk0dcm" MAXDELAY = 0.450ns;
NET "%sinfrastructure_top0/clk_dcm0/clk90dcm" MAXDELAY = 0.450ns;
NET "%sinfrastructure_top0/clk_dcm0/clk0d2inv" MAXDELAY = 0.755ns;
NET "%sinfrastructure_top0/clk_dcm0/clk90d2inv" MAXDELAY = 0.755ns;