generic_ucf.txt

XILINX memory interface generator. XILINX的外部存储器接口。

INST1_var "infrastructure_top0/wait_200us*" TNM = "wait200us";
INST1_var  "infrastructure_top0/wait_clk90" TNM = "wait200us90";
INST1_var  "infrastructure_top0/sys_rst*" TNM = "sysrst";


TIMESPEC TS01 =  FROM  "wait200us"  TO  "sysrst"   TIG;

TIMESPEC TS02 =  FROM  "wait200us90"  TO  "sysrst"   TIG;

TIMESPEC TS05 =  FROM  "wait200us"  TO  "wait200us90"   TIG;


#NET "*/ddr1_top0/reset90_r" TIG;
NET "*/controller0/rst_calib*" TIG;
#INST "*/ddr1_top0/infrastructure0/delay_sel_val*" TIG;
#INST "*/ddr1_top0/infrastructure0/rst_calib*" TIG;
#INST "*/cal_top0/cal_ctl0/un1_tapForDqs*" TIG;
NET "reset_in" TIG;
NET "sys_rst*" TIG;
NET "*/controller0/rst0*" TIG;
NET "*/controller0/rst180*" TIG;
INST "*/data_path0/data_read_controller0/dqs_delay*_col*" TIG;
#INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delayed*" TIG;


#############################################################################
# Calibration Circuit Constraints                                                                              #  
#############################################################################

NET "%sinfrastructure_top0/cal_top0/seltap(4)" S;

NET "%sinfrastructure_top0/cal_top0/ckt_to_cal/delay1" KEEP;
NET "%sinfrastructure_top0/cal_top0/ckt_to_cal/delay2" KEEP;
NET "%sinfrastructure_top0/cal_top0/ckt_to_cal/delay3" KEEP;
NET "%sinfrastructure_top0/cal_top0/ckt_to_cal/delay4" KEEP;
NET "%sinfrastructure_top0/cal_top0/ckt_to_cal/delay5" KEEP;