mem_interface_top.sdc

XILINX memory interface generator. XILINX的外部存储器接口。

set_attribute -design rtl -name HIERARCHY -value "preserve" -instance ddr1_test0/ddr1_top0/iobs0/datapath_iobs0/ddr_dq_iob30
set_attribute -design rtl -name HIERARCHY -value "preserve" -instance ddr1_test0/ddr1_top0/iobs0/datapath_iobs0/ddr_dq_iob31
set_attribute -design rtl -name HIERARCHY -value "preserve" -instance ddr1_test0/ddr1_top0/iobs0/datapath_iobs0/ddr_dqs_iob4
set_attribute -design rtl -name HIERARCHY -value "preserve" -instance ddr1_test0/ddr1_top0/iobs0/datapath_iobs0/ddr_dqs_iob5
set_attribute -design rtl -name HIERARCHY -value "preserve" -instance ddr1_test0/ddr1_top0/iobs0/datapath_iobs0/ddr_dqs_iob6
set_attribute -design rtl -name HIERARCHY -value "preserve" -instance ddr1_test0/ddr1_top0/iobs0/datapath_iobs0/ddr_dqs_iob7
set_attribute -design rtl -name HIERARCHY -value "preserve" -instance ddr1_test0/ddr1_top0/iobs0/datapath_iobs0/ddr_dq_iob32
set_attribute -design rtl -name HIERARCHY -value "preserve" -instance ddr1_test0/ddr1_top0/iobs0/datapath_iobs0/ddr_dq_iob33
set_attribute -design rtl -name HIERARCHY -value "preserve" -instance ddr1_test0/ddr1_top0/iobs0/datapath_iobs0/ddr_dq_iob34
set_attribute -design rtl -name HIERARCHY -value "preserve" -instance ddr1_test0/ddr1_top0/iobs0/datapath_iobs0/ddr_dq_iob35
set_attribute -design rtl -name HIERARCHY -value "preserve" -instance ddr1_test0/ddr1_top0/iobs0/datapath_iobs0/ddr_dq_iob36
set_attribute -design rtl -name HIERARCHY -value "preserve" -instance ddr1_test0/ddr1_top0/iobs0/datapath_iobs0/ddr_dq_iob37
set_attribute -design rtl -name HIERARCHY -value "preserve" -instance ddr1_test0/ddr1_top0/iobs0/datapath_iobs0/ddr_dq_iob38
set_attribute -design rtl -name HIERARCHY -value "preserve" -instance ddr1_test0/ddr1_top0/iobs0/datapath_iobs0/ddr_dq_iob39
set_attribute -design rtl -name HIERARCHY -value "preserve" -instance ddr1_test0/ddr1_top0/iobs0/datapath_iobs0/ddr_dq_iob40
set_attribute -design rtl -name HIERARCHY -value "preserve" -instance ddr1_test0/ddr1_top0/iobs0/datapath_iobs0/ddr_dq_iob41
set_attribute -design rtl -name HIERARCHY -value "preserve" -instance ddr1_test0/ddr1_top0/iobs0/datapath_iobs0/ddr_dq_iob42
set_attribute -design rtl -name HIERARCHY -value "preserve" -instance ddr1_test0/ddr1_top0/iobs0/datapath_iobs0/ddr_dq_iob43
set_attribute -design rtl -name HIERARCHY -value "preserve" -instance ddr1_test0/ddr1_top0/iobs0/datapath_iobs0/ddr_dq_iob44
set_attribute -design rtl -name HIERARCHY -value "preserve" -instance ddr1_test0/ddr1_top0/iobs0/datapath_iobs0/ddr_dq_iob45
set_attribute -design rtl -name HIERARCHY -value "preserve" -instance ddr1_test0/ddr1_top0/iobs0/datapath_iobs0/ddr_dq_iob46
set_attribute -design rtl -name HIERARCHY -value "preserve" -instance ddr1_test0/ddr1_top0/iobs0/datapath_iobs0/ddr_dq_iob47
set_attribute -design rtl -name HIERARCHY -value "preserve" -instance ddr1_test0/ddr1_top0/iobs0/datapath_iobs0/ddr_dq_iob48
set_attribute -design rtl -name HIERARCHY -value "preserve" -instance ddr1_test0/ddr1_top0/iobs0/datapath_iobs0/ddr_dq_iob49
set_attribute -design rtl -name HIERARCHY -value "preserve" -instance ddr1_test0/ddr1_top0/iobs0/datapath_iobs0/ddr_dq_iob50
set_attribute -design rtl -name HIERARCHY -value "preserve" -instance ddr1_test0/ddr1_top0/iobs0/datapath_iobs0/ddr_dq_iob51
set_attribute -design rtl -name HIERARCHY -value "preserve" -instance ddr1_test0/ddr1_top0/iobs0/datapath_iobs0/ddr_dq_iob52
set_attribute -design rtl -name HIERARCHY -value "preserve" -instance ddr1_test0/ddr1_top0/iobs0/datapath_iobs0/ddr_dq_iob53
set_attribute -design rtl -name HIERARCHY -value "preserve" -instance ddr1_test0/ddr1_top0/iobs0/datapath_iobs0/ddr_dq_iob54
set_attribute -design rtl -name HIERARCHY -value "preserve" -instance ddr1_test0/ddr1_top0/iobs0/datapath_iobs0/ddr_dq_iob55
set_attribute -design rtl -name HIERARCHY -value "preserve" -instance ddr1_test0/ddr1_top0/iobs0/datapath_iobs0/ddr_dq_iob56
set_attribute -design rtl -name HIERARCHY -value "preserve" -instance ddr1_test0/ddr1_top0/iobs0/datapath_iobs0/ddr_dq_iob57
set_attribute -design rtl -name HIERARCHY -value "preserve" -instance ddr1_test0/ddr1_top0/iobs0/datapath_iobs0/ddr_dq_iob58
set_attribute -design rtl -name HIERARCHY -value "preserve" -instance ddr1_test0/ddr1_top0/iobs0/datapath_iobs0/ddr_dq_iob59
set_attribute -design rtl -name HIERARCHY -value "preserve" -instance ddr1_test0/ddr1_top0/iobs0/datapath_iobs0/ddr_dq_iob60
set_attribute -design rtl -name HIERARCHY -value "preserve" -instance ddr1_test0/ddr1_top0/iobs0/datapath_iobs0/ddr_dq_iob61
set_attribute -design rtl -name HIERARCHY -value "preserve" -instance ddr1_test0/ddr1_top0/iobs0/datapath_iobs0/ddr_dq_iob62
set_attribute -design rtl -name HIERARCHY -value "preserve" -instance ddr1_test0/ddr1_top0/iobs0/datapath_iobs0/ddr_dq_iob63





#################################################################################################

################################
# Preserve instantiated LUT4's #
################################

#set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_test_bench0.INST1
#set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_test_bench0.INST_2
#set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_test_bench0.INST3
#set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_test_bench0.INST5
#set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_test_bench0.INST6



set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance infrastructure_top0.cal_top0.ckt_to_cal.one
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance infrastructure_top0.cal_top0.ckt_to_cal.two
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance infrastructure_top0.cal_top0.ckt_to_cal.three
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance infrastructure_top0.cal_top0.ckt_to_cal.four
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance infrastructure_top0.cal_top0.ckt_to_cal.five
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance infrastructure_top0.cal_top0.ckt_to_cal.six

#set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance infrastructure_top0.cal_top0

set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay0_col0.one
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay0_col0.two
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay0_col0.three
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay0_col0.four
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay0_col0.five
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay0_col0.six

#set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read0.ddr1_dqbit0


set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay0_col1.one
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay0_col1.two
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay0_col1.three
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay0_col1.four
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay0_col1.five
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay0_col1.six

##################
# Clocks
##################
#create_clock  -design rtl  -domain Design_Clock -name Design_Clock -period 10.000000 -waveform { 0.000000 5.000000 }
#create_clock  -design rtl { sys_clk_ibuf } -domain ClockDomain0 -name sys_clk_ibuf -period 10.000000 -waveform { 0.000000 5.000000 }

##################
# Input delays
##################
#set_input_delay -design rtl 0.000 -clock Design_Clock -add_delay  {ddr1_dqs(*) dip1 dip3}
#set_input_delay -design rtl 0.000 -clock sys_clk_ibuf -add_delay  {dip2 reset_in user_data_mask(*)}

###################
# Output delays
###################
#set_output_delay -design rtl -11.000 -clock sys_clk_ibuf -min  -add_delay  {ddr1_address(0) ddr1_address(1) ddr1_address(10) ddr1_address(2) ddr1_address(3) ddr1_address(4) ddr1_address(5) ddr1_address(6) ddr1_address(7) ddr1_address(8) ddr1_ba(0) ddr1_casb ddr1_clk0 ddr1_clk0b ddr1_clk1 ddr1_clk1b ddr1_dqs(*) ddr1_rasb ddr1_web}
#set_output_delay -design rtl -33.000 -clock sys_clk_ibuf -min  -add_delay  {ddr1_dm(*) ddr1_dq(*)}
#set_output_delay -design rtl 0.000 -clock Design_Clock -add_delay  {ddr1_address(11) ddr1_address(12) ddr1_address(9) ddr1_cke ddr1_csb}
#set_output_delay -design rtl 0.000 -clock sys_clk_ibuf -add_delay  {ddr1_ba(1) led_error_output1 rst_dqs_div_out}
#set_output_delay -design rtl 0.000 -clock sys_clk_ibuf -max  -add_delay  {ddr1_address(0) ddr1_address(1) ddr1_address(10) ddr1_address(2) ddr1_address(3) ddr1_address(4) ddr1_address(5) ddr1_address(6) ddr1_address(7) ddr1_address(8) ddr1_ba(0) ddr1_casb ddr1_clk0 ddr1_clk0b ddr1_clk1 ddr1_clk1b ddr1_dm(*) ddr1_dq(*) ddr1_dqs(*) ddr1_rasb ddr1_web}