mem_interface_top.sdc

XILINX memory interface generator. XILINX的外部存储器接口。

set_attribute -design rtl -name HIERARCHY -value "preserve" -instance ddr1_test0/ddr1_top0/iobs0/datapath_iobs0/ddr_dq_iob70
set_attribute -design rtl -name HIERARCHY -value "preserve" -instance ddr1_test0/ddr1_top0/iobs0/datapath_iobs0/ddr_dq_iob71
set_attribute -design rtl -name HIERARCHY -value "preserve" -instance ddr1_test0/ddr1_top0/iobs0/datapath_iobs0/ddr_dm0



set_attribute -design rtl -name HIERARCHY -value "preserve" -instance ddr1_test0/ddr1_test_bench0
set_attribute -design rtl -name HIERARCHY -value "preserve" -instance ddr1_test0/ddr1_test_bench0/INST1
set_attribute -design rtl -name HIERARCHY -value "preserve" -instance ddr1_test0/ddr1_test_bench0/INST_2
set_attribute -design rtl -name HIERARCHY -value "preserve" -instance ddr1_test0/ddr1_test_bench0/INST3
set_attribute -design rtl -name HIERARCHY -value "preserve" -instance ddr1_test0/ddr1_test_bench0/INST5
set_attribute -design rtl -name HIERARCHY -value "preserve" -instance ddr1_test0/ddr1_test_bench0/INST6





################################
# Preserve instantiated LUT4's #
################################
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance infrastructure_top0.cal_top0.tap_dly0.l0
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance infrastructure_top0.cal_top0.tap_dly0.l1
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance infrastructure_top0.cal_top0.tap_dly0.l2
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance infrastructure_top0.cal_top0.tap_dly0.l3
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance infrastructure_top0.cal_top0.tap_dly0.l4
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance infrastructure_top0.cal_top0.tap_dly0.l5
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance infrastructure_top0.cal_top0.tap_dly0.l6
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance infrastructure_top0.cal_top0.tap_dly0.l7
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance infrastructure_top0.cal_top0.tap_dly0.l8
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance infrastructure_top0.cal_top0.tap_dly0.l9
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance infrastructure_top0.cal_top0.tap_dly0.l1*
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance infrastructure_top0.cal_top0.tap_dly0.l2*
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance infrastructure_top0.cal_top0.tap_dly0.l3*

set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.controller0

set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay0_col1.one
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay0_col1.two
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay0_col1.three
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay0_col1.four
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay0_col1.five
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay0_col1.six

set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay1_col1.one
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay1_col1.two
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay1_col1.three
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay1_col1.four
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay1_col1.five
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay1_col1.six

set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay2_col1.one
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay2_col1.two
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay2_col1.three
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay2_col1.four
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay2_col1.five
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay2_col1.six

set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay3_col1.one
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay3_col1.two
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay3_col1.three
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay3_col1.four
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay3_col1.five
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay3_col1.six

set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay4_col1.one
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay4_col1.two
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay4_col1.three
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay4_col1.four
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay4_col1.five
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay4_col1.six

set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay5_col1.one
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay5_col1.two
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay5_col1.three
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay5_col1.four
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay5_col1.five
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay5_col1.six

set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay6_col1.one
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay6_col1.two
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay6_col1.three
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay6_col1.four
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay6_col1.five
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay6_col1.six

set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay7_col1.one
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay7_col1.two
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay7_col1.three
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay7_col1.four
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay7_col1.five
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay7_col1.six

set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay8_col1.one
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay8_col1.two
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay8_col1.three
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay8_col1.four
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay8_col1.five
set_attribute -design rtl -name DONT_TOUCH -value TRUE -instance ddr1_test0.ddr1_top0.data_path0.data_read_controller0.dqs_delay8_col1.six