📄 mem_interface_top.ucf
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NET "cntrl0_ddr1_clk2b" LOC = "Y34" ;
NET "cntrl0_ddr1_dm(0)" LOC = "AJ27" ;
NET "cntrl0_ddr1_dm(1)" LOC = "AJ28" ;
NET "cntrl0_ddr1_dm(2)" LOC = "AC25" ;
NET "cntrl0_ddr1_dm(3)" LOC = "AC26" ;
NET "cntrl0_ddr1_dm(4)" LOC = "AG33" ;
NET "cntrl0_ddr1_dm(5)" LOC = "AC29" ;
NET "cntrl0_ddr1_dm(6)" LOC = "AB27" ;
NET "cntrl0_ddr1_dm(7)" LOC = "AB28" ;
#NET "cntrl0_ddr1_csb" LOC = "AE30" ;
NET "reset_in" LOC = "H26" ;
NET "cntrl0_ddr1_csb" LOC = "W31" ;
#NET "cntrl0_ddr1_csb" LOC = "W32" ;
NET "cntrl0_ddr1_rasb" LOC = "U28" ;
NET "cntrl0_ddr1_casb" LOC = "U27" ;
NET "cntrl0_ddr1_web" LOC = "V33" ;
NET "cntrl0_ddr1_cke" LOC = "R34" ;
NET "cntrl0_ddr1_ba(0)" LOC = "R29" ;
NET "cntrl0_ddr1_ba(1)" LOC = "R28" ;
NET "cntrl0_ddr1_address(0)" LOC = "P28" ;
NET "cntrl0_ddr1_address(1)" LOC = "P27" ;
NET "cntrl0_ddr1_address(2)" LOC = "N34" ;
NET "cntrl0_ddr1_address(3)" LOC = "N30" ;
NET "cntrl0_ddr1_address(4)" LOC = "N29" ;
NET "cntrl0_ddr1_address(6)" LOC = "L34" ;
NET "cntrl0_ddr1_address(7)" LOC = "K34" ;
NET "cntrl0_ddr1_address(8)" LOC = "L30" ;
NET "cntrl0_ddr1_address(9)" LOC = "L29" ;
NET "cntrl0_ddr1_address(5)" LOC = "L28" ;
NET "cntrl0_ddr1_address(10)" LOC = "J28" ;
NET "cntrl0_ddr1_address(11)" LOC = "J27" ;
NET "cntrl0_ddr1_address(12)" LOC = "E34" ;
#########################################################################
# MAXDELAY constraints #
#########################################################################
NET "*/ddr1_top0/data_path0/data_read0/fbit_0(*)" MAXDELAY = 1200ps;
NET "*/ddr1_top0/data_path0/data_read0/fbit_1(*)" MAXDELAY = 1200ps;
NET "*/ddr1_top0/data_path0/data_read0/fbit_2(*)" MAXDELAY = 1200ps;
NET "*/ddr1_top0/data_path0/data_read0/fbit_3(*)" MAXDELAY = 1200ps;
NET "*/ddr1_top0/controller0/rst_dqs_div_int" MAXDELAY = 600ps ;
NET "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delayed" MAXDELAY = 1500ps;
NET "*/ddr1_top0/data_path0/data_read_controller0/fifo_*_wr_addr*" MAXDELAY = 3000ps;
NET "*/ddr1_top0/data_path0/data_read0/fifo_*_rd_addr*" MAXDELAY = 3000ps;
NET "*/ddr1_top0/data_path0/data_read_controller0/transfer_done_*" MAXDELAY = 1500ps;
#########################################################################
########################################################################
NET "cntrl0_rst_dqs_div_in" LOC = "U29";
NET "cntrl0_rst_dqs_div_out" LOC = "U30";
INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delay0/one" LOC = SLICE_X0Y60;
INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delay0/one" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delay0/two" LOC = SLICE_X0Y61;
INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delay0/two" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delay0/three" LOC = SLICE_X0Y61;
INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delay0/three" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delay0/four" LOC = SLICE_X1Y60;
INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delay0/four" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delay0/five" LOC = SLICE_X1Y60;
INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delay0/five" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delay0/six" LOC = SLICE_X1Y61;
INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delay0/six" BEL = G;
#############################################################
## constraints for bit ddr1_dqs, 0
NET "cntrl0_ddr1_dqs(0)" LOC = AK31;
## LUT location constraints for col 0
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/one" LOC = SLICE_X2Y2;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/one" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/two" LOC = SLICE_X2Y3;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/two" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/three" LOC = SLICE_X2Y3;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/three" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/four" LOC = SLICE_X3Y2;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/four" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/five" LOC = SLICE_X3Y2;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/five" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/six" LOC = SLICE_X3Y3;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/six" BEL = G;
## LUT location constraints for col 1
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/one" LOC = SLICE_X0Y2;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/one" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/two" LOC = SLICE_X0Y3;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/two" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/three" LOC = SLICE_X0Y3;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/three" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/four" LOC = SLICE_X1Y2;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/four" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/five" LOC = SLICE_X1Y2;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/five" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/six" LOC = SLICE_X1Y3;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/six" BEL = G;
#############################################################
## constraints for bit ddr1_dq, 0
NET "cntrl0_ddr1_dq(0)" LOC = AH29;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit0/fbit0" RLOC_ORIGIN = X0Y4;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit0/fbit0" RLOC = X0Y1;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit0/fbit0" BEL = "FFX";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit0/fbit0" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit0/dq";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit0/fbit2" RLOC = X1Y1;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit0/fbit2" BEL = "FFX";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit0/fbit2" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit0/dq";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit0/fbit1" RLOC = X3Y1;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit0/fbit1" BEL = "FFX";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit0/fbit1" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit0/dq";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit0/fbit3" RLOC = X2Y1;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit0/fbit3" BEL = "FFX";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit0/fbit3" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit0/dq";
#############################################################
## constraints for bit ddr1_dq, 1
NET "cntrl0_ddr1_dq(1)" LOC = AH30;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit1/fbit0" RLOC = X0Y1;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit1/fbit0" BEL = "FFY";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit1/fbit0" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit0/dq";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit1/fbit2" RLOC = X1Y1;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit1/fbit2" BEL = "FFY";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit1/fbit2" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit0/dq";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit1/fbit1" RLOC = X3Y1;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit1/fbit1" BEL = "FFY";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit1/fbit1" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit0/dq";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit1/fbit3" RLOC = X2Y1;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit1/fbit3" BEL = "FFY";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit1/fbit3" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit0/dq";
#############################################################
## constraints for bit ddr1_dq, 2
NET "cntrl0_ddr1_dq(2)" LOC = AH27;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit2/fbit0" RLOC = X0Y0;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit2/fbit0" BEL = "FFY";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit2/fbit0" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit0/dq";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit2/fbit2" RLOC = X1Y0;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit2/fbit2" BEL = "FFY";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit2/fbit2" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit0/dq";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit2/fbit1" RLOC = X3Y0;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit2/fbit1" BEL = "FFY";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit2/fbit1" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit0/dq";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit2/fbit3" RLOC = X2Y0;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit2/fbit3" BEL = "FFY";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit2/fbit3" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit0/dq";
#############################################################
## constraints for bit ddr1_dq, 3
NET "cntrl0_ddr1_dq(3)" LOC = AG28;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit3/fbit0" RLOC = X0Y0;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit3/fbit0" BEL = "FFX";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit3/fbit0" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit0/dq";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit3/fbit2" RLOC = X1Y0;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit3/fbit2" BEL = "FFX";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit3/fbit2" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit0/dq";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit3/fbit1" RLOC = X3Y0;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit3/fbit1" BEL = "FFX";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit3/fbit1" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit0/dq";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit3/fbit3" RLOC = X2Y0;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit3/fbit3" BEL = "FFX";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit3/fbit3" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit0/dq";
#############################################################
## constraints for bit ddr1_dq, 4
NET "cntrl0_ddr1_dq(4)" LOC = AL33;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit4/fbit0" RLOC_ORIGIN = X0Y6;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit4/fbit0" RLOC = X0Y0;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit4/fbit0" BEL = "FFY";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit4/fbit0" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit4/dq";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit4/fbit2" RLOC = X1Y0;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit4/fbit2" BEL = "FFY";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit4/fbit2" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit4/dq";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit4/fbit1" RLOC = X3Y0;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit4/fbit1" BEL = "FFY";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit4/fbit1" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit4/dq";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit4/fbit3" RLOC = X2Y0;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit4/fbit3" BEL = "FFY";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit4/fbit3" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit4/dq";
#############################################################
## constraints for bit ddr1_dq, 5
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