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📄 mem_interface_top.ucf

📁 XILINX memory interface generator. XILINX的外部存储器接口。
💻 UCF
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NET  "cntrl0_ddr1_dq(5)" LOC = AL34;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit5/fbit0" RLOC = X0Y0;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit5/fbit0" BEL = "FFX";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit5/fbit0" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit4/dq";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit5/fbit2" RLOC = X1Y0;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit5/fbit2" BEL = "FFX";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit5/fbit2" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit4/dq";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit5/fbit1" RLOC = X3Y0;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit5/fbit1" BEL = "FFX";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit5/fbit1" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit4/dq";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit5/fbit3" RLOC = X2Y0;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit5/fbit3" BEL = "FFX";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit5/fbit3" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit4/dq";
#############################################################
##  constraints for bit ddr1_dq, 6
NET  "cntrl0_ddr1_dq(6)" LOC = AF31;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit6/fbit0" RLOC_ORIGIN = X0Y8;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit6/fbit0" RLOC = X0Y1;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit6/fbit0" BEL = "FFX";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit6/fbit0" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit6/dq";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit6/fbit2" RLOC = X1Y1;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit6/fbit2" BEL = "FFX";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit6/fbit2" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit6/dq";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit6/fbit1" RLOC = X3Y1;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit6/fbit1" BEL = "FFX";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit6/fbit1" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit6/dq";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit6/fbit3" RLOC = X2Y1;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit6/fbit3" BEL = "FFX";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit6/fbit3" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit6/dq";
#############################################################
##  constraints for bit ddr1_dq, 7
NET  "cntrl0_ddr1_dq(7)" LOC = AF32;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit7/fbit0" RLOC = X0Y1;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit7/fbit0" BEL = "FFY";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit7/fbit0" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit6/dq";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit7/fbit2" RLOC = X1Y1;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit7/fbit2" BEL = "FFY";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit7/fbit2" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit6/dq";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit7/fbit1" RLOC = X3Y1;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit7/fbit1" BEL = "FFY";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit7/fbit1" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit6/dq";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit7/fbit3" RLOC = X2Y1;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit7/fbit3" BEL = "FFY";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit7/fbit3" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit6/dq";
#############################################################
##  constraints for bit no_dpin, 0
INST "*/ddr1_top0/data_path0/data_read_controller0/ddr1_dqs_div0/col0" LOC = SLICE_X3Y11;
INST "*/ddr1_top0/data_path0/data_read_controller0/ddr1_dqs_div0/col1" LOC = SLICE_X1Y11;
NET "*/ddr1_top0/data_path0/data_read_controller0/ddr1_dqs_div0/dqs_divn" MAXDELAY = 1200ps;
NET "*/ddr1_top0/data_path0/data_read_controller0/ddr1_dqs_div0/dqs_divp" MAXDELAY = 1200ps;
INST "*/ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone0_clk0" LOC = SLICE_X1Y10;
INST "*/ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone0_clk0" BEL = FFX;
INST "*/ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone0_clk90" LOC = SLICE_X3Y10;
INST "*/ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone0_clk90" BEL = FFX;
INST "*/ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone0_rst90" LOC = SLICE_X3Y10;
INST "*/ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone0_rst90" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone0_clk180" LOC = SLICE_X0Y11;
INST "*/ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone0_clk180" BEL = FFX;
INST "*/ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone0_clk270" LOC = SLICE_X2Y11;
INST "*/ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone0_clk270" BEL = FFX;
INST "*/ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone0_rst270" LOC = SLICE_X2Y11;
INST "*/ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone0_rst270" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone0" LOC = SLICE_X2Y11;
INST "*/ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone0" BEL = F;

INST "*/ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone1_clk270" LOC = SLICE_X5Y11;
INST "*/ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone1_clk270" BEL = FFX;
INST "*/ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone2_clk270" LOC = SLICE_X5Y11;
INST "*/ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone2_clk270" BEL = FFY;
INST "*/ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone1_clk90" LOC = SLICE_X5Y10;
INST "*/ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone1_clk90" BEL = FFX;
INST "*/ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone2_clk90" LOC = SLICE_X5Y10;
INST "*/ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone2_clk90" BEL = FFY;
INST "*/ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone1" LOC = SLICE_X5Y10;
INST "*/ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone1" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone2" LOC = SLICE_X5Y10;
INST "*/ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone2" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone3_clk90" LOC = SLICE_X4Y11;
INST "*/ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone3_clk90" BEL = FFX;
INST "*/ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone3_clk270" LOC = SLICE_X4Y10;
INST "*/ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone3_clk270" BEL = FFX;
INST "*/ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone3" LOC = SLICE_X4Y10;
INST "*/ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone3" BEL = F;
#############################################################
##  constraints for bit ddr1_dqs, 1
NET  "cntrl0_ddr1_dqs(1)" LOC = AD27;
## LUT location constraints for col 0
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col0/one" LOC = SLICE_X2Y12;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col0/one" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col0/two" LOC = SLICE_X2Y13;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col0/two" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col0/three" LOC = SLICE_X2Y13;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col0/three" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col0/four" LOC = SLICE_X3Y12;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col0/four" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col0/five" LOC = SLICE_X3Y12;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col0/five" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col0/six" LOC = SLICE_X3Y13;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col0/six" BEL = G;

## LUT location constraints for col 1
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col1/one" LOC = SLICE_X0Y12;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col1/one" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col1/two" LOC = SLICE_X0Y13;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col1/two" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col1/three" LOC = SLICE_X0Y13;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col1/three" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col1/four" LOC = SLICE_X1Y12;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col1/four" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col1/five" LOC = SLICE_X1Y12;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col1/five" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col1/six" LOC = SLICE_X1Y13;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col1/six" BEL = G;
#############################################################
##  constraints for bit ddr1_dq, 8
NET  "cntrl0_ddr1_dq(8)" LOC = AF33;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit8/fbit0" RLOC_ORIGIN = X0Y14;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit8/fbit0" RLOC = X0Y0;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit8/fbit0" BEL = "FFY";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit8/fbit0" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit8/dq";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit8/fbit2" RLOC = X1Y0;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit8/fbit2" BEL = "FFY";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit8/fbit2" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit8/dq";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit8/fbit1" RLOC = X3Y0;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit8/fbit1" BEL = "FFY";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit8/fbit1" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit8/dq";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit8/fbit3" RLOC = X2Y0;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit8/fbit3" BEL = "FFY";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit8/fbit3" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit8/dq";
#############################################################
##  constraints for bit ddr1_dq, 9
NET  "cntrl0_ddr1_dq(9)" LOC = AE33;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit9/fbit0" RLOC = X0Y0;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit9/fbit0" BEL = "FFX";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit9/fbit0" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit8/dq";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit9/fbit2" RLOC = X1Y0;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit9/fbit2" BEL = "FFX";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit9/fbit2" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit8/dq";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit9/fbit1" RLOC = X3Y0;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit9/fbit1" BEL = "FFX";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit9/fbit1" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit8/dq";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit9/fbit3" RLOC = X2Y0;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit9/fbit3" BEL = "FFX";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit9/fbit3" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit8/dq";
#############################################################
##  constraints for bit ddr1_dq, 10
NET  "cntrl0_ddr1_dq(10)" LOC = AD29;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit10/fbit0" RLOC_ORIGIN = X0Y16;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit10/fbit0" RLOC = X0Y1;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit10/fbit0" BEL = "FFX";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit10/fbit0" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit10/dq";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit10/fbit2" RLOC = X1Y1;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit10/fbit2" BEL = "FFX";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit10/fbit2" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit10/dq";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit10/fbit1" RLOC = X3Y1;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit10/fbit1" BEL = "FFX";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit10/fbit1" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit10/dq";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit10/fbit3" RLOC = X2Y1;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit10/fbit3" BEL = "FFX";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit10/fbit3" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit10/dq";
#############################################################
##  constraints for bit ddr1_dq, 11
NET  "cntrl0_ddr1_dq(11)" LOC = AD30;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit11/fbit0" RLOC = X0Y1;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit11/fbit0" BEL = "FFY";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit11/fbit0" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit10/dq";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit11/fbit2" RLOC = X1Y1;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit11/fbit2" BEL = "FFY";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit11/fbit2" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit10/dq";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit11/fbit1" RLOC = X3Y1;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit11/fbit1" BEL = "FFY";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit11/fbit1" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit10/dq";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit11/fbit3" RLOC = X2Y1;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit11/fbit3" BEL = "FFY";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit11/fbit3" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit10/dq";
#############################################################
##  constraints for bit ddr1_dq, 12
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