mem_interface_top.ucf

XILINX memory interface generator. XILINX的外部存储器接口。

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##
##  Xilinx, Inc. 2005            www.xilinx.com  
##  Fri May 6 12:12:96 2005
##
##  
############################################################################
##  File name :       ddr1_test.ucf
## 
##  Description :     Constraints file
##                    targetted to xc2vp20-6 ff1152 
##
############################################################################

############################################################################
# Clock constraints                                                        #
############################################################################
NET "sys_clk_ibuf" TNM_NET = FFS(*) "SYS_CLK";
TIMESPEC "TS_SYS_CLK" = PERIOD "SYS_CLK"  5.0000  ns HIGH 50 %;

############################################################################
############################################################################

## I/O STANDARDS                 
############################################################################
NET "SYS_CLK*"                        IOSTANDARD = LVDS_25; 
NET "reset_in"                        IOSTANDARD = LVCMOS25; 

############################################################################

############################################################################
# Banks 4
# Pin Location Constraints for System clock and system controls 
 ############################################################################
NET  "SYS_CLKb"               LOC = "AL18";#NET  "SYS_CLKb"               LOC = "AL18";#
NET  "SYS_CLK"                LOC = "AK18";#NET  "SYS_CLK"                LOC = "AK18";#
NET "infrastructure_top0/wait_200us" TNM = "wait200us";
NET "infrastructure_top0/wait_clk90" TNM = "wait200us90";
NET "infrastructure_top0/sys_rst*" TNM = "sysrst";


TIMESPEC TS01 =  FROM  "wait200us"  TO  "sysrst"   TIG;

TIMESPEC TS02 =  FROM  "wait200us90"  TO  "sysrst"   TIG;

TIMESPEC TS05 =  FROM  "wait200us"  TO  "wait200us90"   TIG;
#############################################################################
# Calibration Circuit Constraints                                                                              #  
#############################################################################

NET "infrastructure_top0/cal_top0/seltap(4)" S;

NET "infrastructure_top0/cal_top0/ckt_to_cal/delay1" KEEP;
NET "infrastructure_top0/cal_top0/ckt_to_cal/delay2" KEEP;
NET "infrastructure_top0/cal_top0/ckt_to_cal/delay3" KEEP;
NET "infrastructure_top0/cal_top0/ckt_to_cal/delay4" KEEP;
NET "infrastructure_top0/cal_top0/ckt_to_cal/delay5" KEEP;




 


############################################################################
# Calibration Circuit Constraints
############################################################################

INST "infrastructure_top0/cal_top0/cal_dcm" LOC="DCM_X2Y0"; 

INST "infrastructure_top0/cal_top0" AREA_GROUP=gp1;
AREA_GROUP "gp1" RANGE = SLICE_X52Y0:SLICE_X75Y11;

INST "infrastructure_top0/cal_top0/cal_clkd2" LOC = SLICE_X72Y0;
INST "infrastructure_top0/cal_top0/cal_phClkd2" LOC = SLICE_X72Y3;

INST "infrastructure_top0/cal_top0/hxSampReg0" LOC = SLICE_X74Y0;


INST "infrastructure_top0/cal_top0/cal_suClkd2" LOC = SLICE_X72Y4;
INST "infrastructure_top0/cal_top0/cal_suPhClkd2" LOC = SLICE_X74Y5;
INST "infrastructure_top0/cal_top0/phSampReg0" LOC = SLICE_X74Y4;
#############################################################
# LUT Location Constraints for dqs_delay Circuit
#############################################################
 INST "infrastructure_top0/cal_top0/ckt_to_cal/one" LOC = SLICE_X74Y2; 
 INST "infrastructure_top0/cal_top0/ckt_to_cal/one" BEL = F; 
 INST "infrastructure_top0/cal_top0/ckt_to_cal/two" LOC = SLICE_X74Y3; 
 INST "infrastructure_top0/cal_top0/ckt_to_cal/two" BEL = F; 
 INST "infrastructure_top0/cal_top0/ckt_to_cal/three" LOC = SLICE_X74Y3; 
 INST "infrastructure_top0/cal_top0/ckt_to_cal/three" BEL = G; 
 INST "infrastructure_top0/cal_top0/ckt_to_cal/four" LOC = SLICE_X75Y2; 
 INST "infrastructure_top0/cal_top0/ckt_to_cal/four" BEL = F; 
 INST "infrastructure_top0/cal_top0/ckt_to_cal/five" LOC = SLICE_X75Y2; 
 INST "infrastructure_top0/cal_top0/ckt_to_cal/five" BEL = G; 
 INST "infrastructure_top0/cal_top0/ckt_to_cal/six" LOC = SLICE_X75Y3; 
 INST "infrastructure_top0/cal_top0/ckt_to_cal/six" BEL = G; 


###no_dcm
############################################################################
# DCM, MACRO and BUFG  Constraints

############################################################################

INST "infrastructure_top0/clk_dcm0/DCM_INST1" LOC="DCM_X3Y0"; 

INST "infrastructure_top0/clk_dcm0/BUFG_CLK0/u1" LOC="BUFGMUX6P";
INST "infrastructure_top0/clk_dcm0/BUFG_CLK90/u1" LOC="BUFGMUX7S";


NET "infrastructure_top0/cal_top0/clkdiv2" MAXDELAY = 600 ps;
NET "infrastructure_top0/cal_top0/phclkdiv2" MAXDELAY = 600 ps;

NET "infrastructure_top0/cal_top0/suclkdiv2" MAXDELAY = 600ps;
NET "infrastructure_top0/cal_top0/suphclkdiv2" MAXDELAY = 700ps;

##############################################################################
# MaxDelay constraints                                                                                                #
##############################################################################

NET "infrastructure_top0/clk_dcm0/clk0dcm" MAXDELAY = 0.450ns;
NET "infrastructure_top0/clk_dcm0/clk90dcm" MAXDELAY = 0.450ns;
NET "infrastructure_top0/clk_dcm0/clk0d2inv" MAXDELAY = 0.755ns;
NET "infrastructure_top0/clk_dcm0/clk90d2inv" MAXDELAY = 0.755ns;



#********************************************************************#
#                        CONTROLLER 0                               #
#********************************************************************#
############################################################################
# I/O STANDARDS                                                         #
############################################################################
# SSTL2_II for input or output signals 
NET "cntrl0_ddr1_dq(*)"                      IOSTANDARD = SSTL2_II; 
NET "cntrl0_ddr1_dqs(*)"                        IOSTANDARD = SSTL2_II;
NET "cntrl0_ddr1_dm(*)"                         IOSTANDARD = SSTL2_II;
NET "cntrl0_ddr1_clk*"                       IOSTANDARD = SSTL2_II; 
NET "cntrl0_ddr1_clk*b"                      IOSTANDARD = SSTL2_II; 
NET "cntrl0_ddr1_address(*)"                 IOSTANDARD = SSTL2_II; 
NET "cntrl0_ddr1_ba(*)"                      IOSTANDARD = SSTL2_II; 
NET "cntrl0_ddr1_rasb"                       IOSTANDARD = SSTL2_II; 
NET "cntrl0_ddr1_casb"                       IOSTANDARD = SSTL2_II; 
NET "cntrl0_ddr1_web"                        IOSTANDARD = SSTL2_II; 
NET "cntrl0_ddr1_csb"                        IOSTANDARD = SSTL2_II; 
NET "cntrl0_ddr1_cke"                        IOSTANDARD = SSTL2_II; 
NET "cntrl0_rst_dqs_div_in"                        IOSTANDARD = SSTL2_II; 
NET "cntrl0_rst_dqs_div_out"                        IOSTANDARD = SSTL2_II; 

NET "cntrl0_led_error_output1"                 IOSTANDARD = LVCMOS25;

############################################################################
# IO Signals Registering Constraints                                           #
############################################################################
INST "*/ddr1_top0/iobs0/data_path_iobs0/ddr_dqs_iob*"  IOB = TRUE;
INST "*/ddr1_top0/iobs0/data_path_iobs0/ddr_dq_iob*"  IOB = TRUE;
INST "*/ddr1_top0/controller0/rst_iob_out"            IOB = TRUE;
INST "*/ddr1_top0/iobs0/controller_iobs0/iob_addr*" IOB = TRUE;
INST "*/ddr1_top0/iobs0/controller_iobs0/iob_ba*" IOB = TRUE;
INST "*/ddr1_top0/iobs0/controller_iobs0/iob_rasb"      IOB = TRUE;
INST "*/ddr1_top0/iobs0/controller_iobs0/iob_casb"      IOB = TRUE;
INST "*/ddr1_top0/iobs0/controller_iobs0/iob_web"     IOB = TRUE;
INST "*/ddr1_top0/iobs0/controller_iobs0/iob_cke"     IOB = TRUE;

############################################################################
# Banks 2367
# Pin Location Constraints for Clock,Masks, Address, and Controls 
 ############################################################################
NET "cntrl0_ddr1_clk0b"             LOC = "F8" ;
NET "cntrl0_ddr1_clk0"             LOC = "F7" ;
NET "cntrl0_ddr1_clk1b"             LOC = "E4" ;
NET "cntrl0_ddr1_clk1"             LOC = "E3" ;
NET "cntrl0_ddr1_clk2b"             LOC = "N6" ;
NET "cntrl0_ddr1_clk2"             LOC = "N5" ;
NET "cntrl0_ddr1_clk3b"             LOC = "AE2" ;
NET "cntrl0_ddr1_clk3"             LOC = "AF2" ;
NET "cntrl0_ddr1_clk4b"             LOC = "AJ7" ;
NET "cntrl0_ddr1_clk4"             LOC = "AJ8" ;