📄 mem_interface_top.ucf
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NET "cntrl0_ddr1_dm(3)" LOC = "J8" ;
NET "cntrl0_ddr1_dm(4)" LOC = "J7" ;
NET "cntrl0_ddr1_dm(0)" LOC = "K2" ;
NET "cntrl0_ddr1_dm(1)" LOC = "L8" ;
NET "cntrl0_ddr1_dm(2)" LOC = "L7" ;
NET "cntrl0_ddr1_dm(5)" LOC = "W8" ;
NET "cntrl0_ddr1_dm(6)" LOC = "AA8" ;
NET "cntrl0_ddr1_dm(7)" LOC = "AB10" ;
NET "cntrl0_ddr1_dm(8)" LOC = "AH8" ;
NET "cntrl0_ddr1_rasb" LOC = "P3" ;
NET "cntrl0_ddr1_casb" LOC = "T11" ;
NET "cntrl0_ddr1_web" LOC = "U11" ;
NET "cntrl0_ddr1_cke" LOC = "R7" ;
NET "cntrl0_ddr1_csb" LOC = "R6" ;
NET "cntrl0_ddr1_ba(0)" LOC = "U10" ;
NET "cntrl0_ddr1_ba(1)" LOC = "U9" ;
#NET "cntrl0_" LOC = "U6" ;
#NET "cntrl0_" LOC = "Y2" ;
NET "cntrl0_ddr1_address(0)" LOC = "U6" ;
NET "cntrl0_ddr1_address(1)" LOC = "U5" ;
NET "cntrl0_ddr1_address(2)" LOC = "Y2" ;
NET "cntrl0_ddr1_address(3)" LOC = "Y6" ;
NET "cntrl0_ddr1_address(4)" LOC = "Y7" ;
NET "cntrl0_ddr1_address(5)" LOC = "AA2" ;
NET "cntrl0_ddr1_address(6)" LOC = "AB2" ;
NET "cntrl0_ddr1_address(7)" LOC = "AB5" ;
NET "cntrl0_ddr1_address(8)" LOC = "AB6" ;
NET "cntrl0_ddr1_address(9)" LOC = "AD2" ;
NET "cntrl0_ddr1_address(10)" LOC = "AD5" ;
NET "cntrl0_ddr1_address(11)" LOC = "AD6" ;
NET "cntrl0_ddr1_address(12)" LOC = "AH5" ;
NET "reset_in" LOC = "H26" ;
NET "cntrl0_led_error_output1" LOC = "L18" ;
#########################################################################
# MAXDELAY constraints #
#########################################################################
NET "*/ddr1_top0/data_path0/data_read0/fbit_0(*)" MAXDELAY = 1200ps;
NET "*/ddr1_top0/data_path0/data_read0/fbit_1(*)" MAXDELAY = 1200ps;
NET "*/ddr1_top0/data_path0/data_read0/fbit_2(*)" MAXDELAY = 1200ps;
NET "*/ddr1_top0/data_path0/data_read0/fbit_3(*)" MAXDELAY = 1200ps;
NET "*/ddr1_top0/controller0/rst_dqs_div_int" MAXDELAY = 600ps ;
NET "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delayed" MAXDELAY = 1500ps;
NET "*/ddr1_top0/data_path0/data_read_controller0/fifo_*_wr_addr*" MAXDELAY = 3000ps;
NET "*/ddr1_top0/data_path0/data_read0/fifo_*_rd_addr*" MAXDELAY = 3000ps;
NET "*/ddr1_top0/data_path0/data_read_controller0/transfer_done_*" MAXDELAY = 1500ps;
#########################################################################
########################################################################
NET "cntrl0_rst_dqs_div_in" LOC = "L6";
NET "cntrl0_rst_dqs_div_out" LOC = "L5";
INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delay0/one" LOC = SLICE_X90Y96;
INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delay0/one" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delay0/two" LOC = SLICE_X90Y97;
INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delay0/two" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delay0/three" LOC = SLICE_X90Y97;
INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delay0/three" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delay0/four" LOC = SLICE_X91Y96;
INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delay0/four" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delay0/five" LOC = SLICE_X91Y96;
INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delay0/five" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delay0/six" LOC = SLICE_X91Y97;
INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delay0/six" BEL = G;
#############################################################
## constraints for bit ddr1_dqs, 0
INST "cntrl0_ddr1_dqs(0)" LOC = E1;
## LUT location constraints for col 0
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/one" LOC = SLICE_X90Y106;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/one" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/two" LOC = SLICE_X90Y107;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/two" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/three" LOC = SLICE_X90Y107;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/three" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/four" LOC = SLICE_X91Y106;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/four" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/five" LOC = SLICE_X91Y106;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/five" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/six" LOC = SLICE_X91Y107;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/six" BEL = G;
## LUT location constraints for col 1
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/one" LOC = SLICE_X88Y106;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/one" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/two" LOC = SLICE_X88Y107;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/two" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/three" LOC = SLICE_X88Y107;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/three" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/four" LOC = SLICE_X89Y106;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/four" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/five" LOC = SLICE_X89Y106;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/five" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/six" LOC = SLICE_X89Y107;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/six" BEL = G;
#############################################################
## constraints for bit ddr1_dq, 0
INST "cntrl0_ddr1_dq(0)" LOC = F5;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit0/fbit0" RLOC_ORIGIN = X88Y104;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit0/fbit0" RLOC = X0Y1;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit0/fbit0" BEL = "FFY";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit0/fbit0" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit0/dq";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit0/fbit2" RLOC = X1Y1;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit0/fbit2" BEL = "FFY";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit0/fbit2" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit0/dq";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit0/fbit1" RLOC = X3Y1;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit0/fbit1" BEL = "FFY";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit0/fbit1" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit0/dq";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit0/fbit3" RLOC = X2Y1;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit0/fbit3" BEL = "FFY";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit0/fbit3" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit0/dq";
#############################################################
## constraints for bit ddr1_dq, 1
INST "cntrl0_ddr1_dq(1)" LOC = F4;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit1/fbit0" RLOC = X0Y1;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit1/fbit0" BEL = "FFX";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit1/fbit0" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit0/dq";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit1/fbit2" RLOC = X1Y1;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit1/fbit2" BEL = "FFX";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit1/fbit2" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit0/dq";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit1/fbit1" RLOC = X3Y1;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit1/fbit1" BEL = "FFX";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit1/fbit1" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit0/dq";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit1/fbit3" RLOC = X2Y1;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit1/fbit3" BEL = "FFX";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit1/fbit3" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit0/dq";
#############################################################
## constraints for bit ddr1_dq, 2
INST "cntrl0_ddr1_dq(2)" LOC = H2;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit2/fbit0" RLOC_ORIGIN = X88Y102;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit2/fbit0" RLOC = X0Y0;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit2/fbit0" BEL = "FFX";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit2/fbit0" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit2/dq";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit2/fbit2" RLOC = X1Y0;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit2/fbit2" BEL = "FFX";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit2/fbit2" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit2/dq";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit2/fbit1" RLOC = X3Y0;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit2/fbit1" BEL = "FFX";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit2/fbit1" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit2/dq";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit2/fbit3" RLOC = X2Y0;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit2/fbit3" BEL = "FFX";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit2/fbit3" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit2/dq";
#############################################################
## constraints for bit ddr1_dq, 3
INST "cntrl0_ddr1_dq(3)" LOC = H1;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit3/fbit0" RLOC = X0Y0;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit3/fbit0" BEL = "FFY";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit3/fbit0" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit2/dq";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit3/fbit2" RLOC = X1Y0;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit3/fbit2" BEL = "FFY";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit3/fbit2" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit2/dq";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit3/fbit1" RLOC = X3Y0;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit3/fbit1" BEL = "FFY";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit3/fbit1" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit2/dq";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit3/fbit3" RLOC = X2Y0;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit3/fbit3" BEL = "FFY";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit3/fbit3" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit2/dq";
#############################################################
## constraints for bit ddr1_dq, 4
INST "cntrl0_ddr1_dq(4)" LOC = M10;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit4/fbit0" RLOC = X0Y1;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit4/fbit0" BEL = "FFY";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit4/fbit0" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit2/dq";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit4/fbit2" RLOC = X1Y1;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit4/fbit2" BEL = "FFY";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit4/fbit2" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit2/dq";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit4/fbit1" RLOC = X3Y1;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit4/fbit1" BEL = "FFY";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit4/fbit1" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit2/dq";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit4/fbit3" RLOC = X2Y1;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit4/fbit3" BEL = "FFY";
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit4/fbit3" U_SET = "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit2/dq";
#############################################################
## constraints for bit ddr1_dq, 5
INST "cntrl0_ddr1_dq(5)" LOC = M9;
INST "*/ddr1_top0/data_path0/data_read0/ddr1_dqbit5/fbit0" RLOC = X0Y1;
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