📄 mem_interface_top.ucf
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NET "*/ddr1_top0/data_path0/user_output_data(*)" MAXDELAY = 3000ps;
NET "*/ddr1_top0/controller0/rst_dqs_div_r" MAXDELAY = 1500ps;
#########################################################################
########################################################################
NET "cntrl0_rst_dqs_div_in" LOC = "L6";
NET "cntrl0_rst_dqs_div_out" LOC = "L5";
INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delayed/one" LOC = SLICE_X90Y96;
INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delayed/one" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delayed/two" LOC = SLICE_X90Y97;
INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delayed/two" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delayed/three" LOC = SLICE_X90Y97;
INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delayed/three" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delayed/four" LOC = SLICE_X91Y96;
INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delayed/four" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delayed/five" LOC = SLICE_X91Y96;
INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delayed/five" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delayed/six" LOC = SLICE_X91Y97;
INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delayed/six" BEL = G;
#############################################################
## constraints for bit ddr1_dqs, 0, location in tile: 2
INST "cntrl0_ddr1_dqs(0)" LOC = E1;
## LUT location constraints for col 0
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/one" LOC = SLICE_X90Y106;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/one" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/two" LOC = SLICE_X90Y107;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/two" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/three" LOC = SLICE_X90Y107;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/three" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/four" LOC = SLICE_X91Y106;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/four" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/five" LOC = SLICE_X91Y106;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/five" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/six" LOC = SLICE_X91Y107;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/six" BEL = G;
## LUT location constraints for col 1
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/one" LOC = SLICE_X88Y106;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/one" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/two" LOC = SLICE_X88Y107;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/two" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/three" LOC = SLICE_X88Y107;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/three" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/four" LOC = SLICE_X89Y106;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/four" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/five" LOC = SLICE_X89Y106;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/five" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/six" LOC = SLICE_X89Y107;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/six" BEL = G;
#############################################################
## constraints for bit ddr1_dq, 0, location in tile: 1
INST "cntrl0_ddr1_dq(0)" LOC = F5;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit0" LOC = SLICE_X90Y105;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit0" BEL = F;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit0" LOC = SLICE_X88Y105;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit0" BEL = F;
#############################################################
## constraints for bit ddr1_dq, 1, location in tile: 0
INST "cntrl0_ddr1_dq(1)" LOC = F4;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit1" LOC = SLICE_X90Y105;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit1" BEL = G;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit1" LOC = SLICE_X88Y105;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit1" BEL = G;
#############################################################
## constraints for bit ddr1_dq, 2, location in tile: 3
INST "cntrl0_ddr1_dq(2)" LOC = H2;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit2" LOC = SLICE_X90Y102;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit2" BEL = F;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit2" LOC = SLICE_X88Y102;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit2" BEL = F;
#############################################################
## constraints for bit ddr1_dq, 3, location in tile: 2
INST "cntrl0_ddr1_dq(3)" LOC = H1;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit3" LOC = SLICE_X90Y102;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit3" BEL = G;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit3" LOC = SLICE_X88Y102;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit3" BEL = G;
#############################################################
## constraints for bit ddr1_dq, 4, location in tile: 1
INST "cntrl0_ddr1_dq(4)" LOC = M10;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit4" LOC = SLICE_X90Y103;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit4" BEL = F;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit4" LOC = SLICE_X88Y103;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit4" BEL = F;
#############################################################
## constraints for bit ddr1_dq, 5, location in tile: 0
INST "cntrl0_ddr1_dq(5)" LOC = M9;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit5" LOC = SLICE_X90Y103;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit5" BEL = G;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit5" LOC = SLICE_X88Y103;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit5" BEL = G;
#############################################################
## constraints for bit ddr1_dq, 6, location in tile: 1
INST "cntrl0_ddr1_dq(6)" LOC = K5;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit6" LOC = SLICE_X90Y101;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit6" BEL = F;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit6" LOC = SLICE_X88Y101;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit6" BEL = F;
#############################################################
## constraints for bit ddr1_dq, 7, location in tile: 0
INST "cntrl0_ddr1_dq(7)" LOC = K4;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit7" LOC = SLICE_X90Y101;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit7" BEL = G;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit7" LOC = SLICE_X88Y101;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit7" BEL = G;
#############################################################
## constraints for bit no_dpin, 0, location in tile: 2
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_00_wr_addr_inst/bit0" LOC = SLICE_X90Y98;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_00_wr_addr_inst/bit1" LOC = SLICE_X90Y98;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_00_wr_addr_inst/bit2" LOC = SLICE_X90Y99;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_00_wr_addr_inst/bit3" LOC = SLICE_X90Y99;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_01_wr_addr_inst/bit0" LOC = SLICE_X88Y98;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_01_wr_addr_inst/bit1" LOC = SLICE_X88Y98;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_01_wr_addr_inst/bit2" LOC = SLICE_X88Y99;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_01_wr_addr_inst/bit3" LOC = SLICE_X88Y99;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_00_wr_en_inst" LOC = SLICE_X91Y98;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_01_wr_en_inst" LOC = SLICE_X89Y98;
#############################################################
## constraints for bit ddr1_dqs, 1, location in tile: 2
INST "cntrl0_ddr1_dqs(1)" LOC = L1;
## LUT location constraints for col 0
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col1/one" LOC = SLICE_X90Y94;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col1/one" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col1/two" LOC = SLICE_X90Y95;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col1/two" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col1/three" LOC = SLICE_X90Y95;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col1/three" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col1/four" LOC = SLICE_X91Y94;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col1/four" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col1/five" LOC = SLICE_X91Y94;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col1/five" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col1/six" LOC = SLICE_X91Y95;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col1/six" BEL = G;
## LUT location constraints for col 1
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col0/one" LOC = SLICE_X88Y94;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col0/one" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col0/two" LOC = SLICE_X88Y95;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col0/two" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col0/three" LOC = SLICE_X88Y95;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col0/three" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col0/four" LOC = SLICE_X89Y94;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col0/four" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col0/five" LOC = SLICE_X89Y94;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col0/five" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col0/six" LOC = SLICE_X89Y95;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col0/six" BEL = G;
#############################################################
## constraints for bit ddr1_dq, 8, location in tile: 1
INST "cntrl0_ddr1_dq(8)" LOC = M7;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit8" LOC = SLICE_X90Y93;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit8" BEL = F;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit8" LOC = SLICE_X88Y93;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit8" BEL = F;
#############################################################
## constraints for bit ddr1_dq, 9, location in tile: 0
INST "cntrl0_ddr1_dq(9)" LOC = M6;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit9" LOC = SLICE_X90Y93;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit9" BEL = G;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit9" LOC = SLICE_X88Y93;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit9" BEL = G;
#############################################################
## constraints for bit ddr1_dq, 10, location in tile: 2
INST "cntrl0_ddr1_dq(10)" LOC = M2;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit10" LOC = SLICE_X90Y90;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit10" BEL = G;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit10" LOC = SLICE_X88Y90;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit10" BEL = G;
#############################################################
## constraints for bit ddr1_dq, 11, location in tile: 1
INST "cntrl0_ddr1_dq(11)" LOC = N8;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit11" LOC = SLICE_X90Y91;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit11" BEL = F;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit11" LOC = SLICE_X88Y91;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit11" BEL = F;
#############################################################
## constraints for bit ddr1_dq, 12, location in tile: 0
INST "cntrl0_ddr1_dq(12)" LOC = N7;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit12" LOC = SLICE_X90Y91;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit12" BEL = G;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit12" LOC = SLICE_X88Y91;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit12" BEL = G;
#############################################################
## constraints for bit ddr1_dq, 13, location in tile: 1
INST "cntrl0_ddr1_dq(13)" LOC = L4;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit13" LOC = SLICE_X90Y89;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit13" BEL = F;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit13" LOC = SLICE_X88Y89;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit13" BEL = F;
#############################################################
## constraints for bit ddr1_dq, 14, location in tile: 0
INST "cntrl0_ddr1_dq(14)" LOC = L3;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit14" LOC = SLICE_X90Y89;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit14" BEL = G;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit14" LOC = SLICE_X88Y89;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit14" BEL = G;
#############################################################
## constraints for bit ddr1_dq, 15, location in tile: 3
INST "cntrl0_ddr1_dq(15)" LOC = M4;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit15" LOC = SLICE_X90Y86;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit15" BEL = G;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit15" LOC = SLICE_X88Y86;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit15" BEL = G;
#############################################################
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