📄 mem_interface_top.ucf
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INST "infrastructure_top0/cal_top0/tap_dly0/r17" U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
INST "infrastructure_top0/cal_top0/tap_dly0/r18" RLOC=X0Y3;
INST "infrastructure_top0/cal_top0/tap_dly0/r18" U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
INST "infrastructure_top0/cal_top0/tap_dly0/r19" RLOC=X0Y3;
INST "infrastructure_top0/cal_top0/tap_dly0/r19" U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
INST "infrastructure_top0/cal_top0/tap_dly0/r20" RLOC=X1Y2;
INST "infrastructure_top0/cal_top0/tap_dly0/r20" U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
INST "infrastructure_top0/cal_top0/tap_dly0/r21" RLOC=X1Y2;
INST "infrastructure_top0/cal_top0/tap_dly0/r21" U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
INST "infrastructure_top0/cal_top0/tap_dly0/r22" RLOC=X1Y3;
INST "infrastructure_top0/cal_top0/tap_dly0/r22" U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
INST "infrastructure_top0/cal_top0/tap_dly0/r23" RLOC=X1Y3;
INST "infrastructure_top0/cal_top0/tap_dly0/r23" U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
INST "infrastructure_top0/cal_top0/tap_dly0/r24" RLOC=X0Y0;
INST "infrastructure_top0/cal_top0/tap_dly0/r24" U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
INST "infrastructure_top0/cal_top0/tap_dly0/r25" RLOC=X0Y0;
INST "infrastructure_top0/cal_top0/tap_dly0/r25" U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
INST "infrastructure_top0/cal_top0/tap_dly0/r26" RLOC=X0Y1;
INST "infrastructure_top0/cal_top0/tap_dly0/r26" U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
INST "infrastructure_top0/cal_top0/tap_dly0/r27" RLOC=X0Y1;
INST "infrastructure_top0/cal_top0/tap_dly0/r27" U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
INST "infrastructure_top0/cal_top0/tap_dly0/r28" RLOC=X1Y0;
INST "infrastructure_top0/cal_top0/tap_dly0/r28" U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
INST "infrastructure_top0/cal_top0/tap_dly0/r29" RLOC=X1Y0;
INST "infrastructure_top0/cal_top0/tap_dly0/r29" U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
INST "infrastructure_top0/cal_top0/tap_dly0/r30" RLOC=X1Y1;
INST "infrastructure_top0/cal_top0/tap_dly0/r30" U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
INST "infrastructure_top0/cal_top0/tap_dly0/r31" RLOC=X1Y1;
INST "infrastructure_top0/cal_top0/tap_dly0/r31" U_SET = "infrastructure_top0/cal_top0/tap_dly0/l0";
#######################################################################################################################
# BEL constraints for luts in tap delay ckt #
#######################################################################################################################
INST "infrastructure_top0/cal_top0/tap_dly0/l0" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l1" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l2" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l3" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l4" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l5" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l6" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l7" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l8" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l9" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l10" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l11" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l12" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l13" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l14" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l15" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l16" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l17" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l18" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l19" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l20" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l21" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l22" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l23" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l24" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l25" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l26" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l27" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l28" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l29" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l30" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l31" BEL= F;
#######################################################################################################################
# Area Group Constraint For tap_dly and cal_ctl module #
#######################################################################################################################
INST "infrastructure_top0/cal_top0/cal_ctl0" AREA_GROUP = cal_ctl;
INST "infrastructure_top0/cal_top0/tap_dly0" AREA_GROUP = cal_ctl;
AREA_GROUP "cal_ctl" RANGE = SLICE_X52Y64:SLICE_X61Y73;
AREA_GROUP "cal_ctl" GROUP = CLOSED;
###no_dcm
#######################################################################################################################
# DCM , MACRO and BUFG constraints #
#######################################################################################################################
INST "infrastructure_top0/clk_dcm0/DCM_INST1" LOC="DCM_X3Y1";
INST "infrastructure_top0/clk_dcm0/BUFG_CLK0/u1" LOC="BUFGMUX6S";
INST "infrastructure_top0/clk_dcm0/BUFG_CLK90/u1" LOC="BUFGMUX7P";
NET "infrastructure_top0/clk_dcm0/clk0dcm" MAXDELAY = 0.450ns;
NET "infrastructure_top0/clk_dcm0/clk90dcm" MAXDELAY = 0.450ns;
NET "infrastructure_top0/clk_dcm0/clk0d2inv" MAXDELAY = 0.755ns;
NET "infrastructure_top0/clk_dcm0/clk90d2inv" MAXDELAY = 0.755ns;
#********************************************************************#
# CONTROLLER 0 #
#********************************************************************#
############################################################################
# I/O STANDARDS #
############################################################################
# SSTL2_II for input or output signals
NET "cntrl0_ddr1_dq(*)" IOSTANDARD = SSTL2_II;
NET "cntrl0_ddr1_dqs(*)" IOSTANDARD = SSTL2_II;
NET "cntrl0_ddr1_dm(*)" IOSTANDARD = SSTL2_II;
NET "cntrl0_ddr1_clk*" IOSTANDARD = SSTL2_II;
NET "cntrl0_ddr1_clk*b" IOSTANDARD = SSTL2_II;
NET "cntrl0_ddr1_address(*)" IOSTANDARD = SSTL2_II;
NET "cntrl0_ddr1_ba(*)" IOSTANDARD = SSTL2_II;
NET "cntrl0_ddr1_rasb" IOSTANDARD = SSTL2_II;
NET "cntrl0_ddr1_casb" IOSTANDARD = SSTL2_II;
NET "cntrl0_ddr1_web" IOSTANDARD = SSTL2_II;
NET "cntrl0_ddr1_csb" IOSTANDARD = SSTL2_II;
NET "cntrl0_ddr1_cke" IOSTANDARD = SSTL2_II;
NET "cntrl0_rst_dqs_div_in" IOSTANDARD = SSTL2_II;
NET "cntrl0_rst_dqs_div_out" IOSTANDARD = SSTL2_II;
NET "cntrl0_led_error_output1" IOSTANDARD = LVCMOS25;
############################################################################
# IO Signals Registering Constraints #
############################################################################
INST "*/ddr1_top0/iobs0/datapath_iobs0/ddr_dqs_iob*" IOB = TRUE;
INST "*/ddr1_top0/iobs0/datapath_iobs0/ddr_dq_iob*" IOB = TRUE;
INST "*/ddr1_top0/controller0/rst_iob_out" IOB = TRUE;
INST "*/ddr1_top0/iobs0/controller_iobs0/iob_addr*" IOB = TRUE;
INST "*/ddr1_top0/iobs0/controller_iobs0/iob_ba*" IOB = TRUE;
INST "*/ddr1_top0/iobs0/controller_iobs0/iob_rasb" IOB = TRUE;
INST "*/ddr1_top0/iobs0/controller_iobs0/iob_casb" IOB = TRUE;
INST "*/ddr1_top0/iobs0/controller_iobs0/iob_web" IOB = TRUE;
INST "*/ddr1_top0/iobs0/controller_iobs0/iob_cke" IOB = TRUE;
############################################################################
# Banks 2367
# Pin Location Constraints for Clock,Masks, Address, and Controls
############################################################################
NET "cntrl0_ddr1_clk0b" LOC = "F8" ;
NET "cntrl0_ddr1_clk0" LOC = "F7" ;
NET "cntrl0_ddr1_clk1b" LOC = "E4" ;
NET "cntrl0_ddr1_clk1" LOC = "E3" ;
NET "cntrl0_ddr1_clk2b" LOC = "N6" ;
NET "cntrl0_ddr1_clk2" LOC = "N5" ;
NET "cntrl0_ddr1_clk3b" LOC = "AE2" ;
NET "cntrl0_ddr1_clk3" LOC = "AF2" ;
NET "cntrl0_ddr1_clk4b" LOC = "AJ7" ;
NET "cntrl0_ddr1_clk4" LOC = "AJ8" ;
NET "cntrl0_ddr1_dm(3)" LOC = "J8" ;
NET "cntrl0_ddr1_dm(4)" LOC = "J7" ;
NET "cntrl0_ddr1_dm(0)" LOC = "K2" ;
NET "cntrl0_ddr1_dm(1)" LOC = "L8" ;
NET "cntrl0_ddr1_dm(2)" LOC = "L7" ;
NET "cntrl0_ddr1_dm(5)" LOC = "W8" ;
NET "cntrl0_ddr1_dm(6)" LOC = "AA8" ;
NET "cntrl0_ddr1_dm(7)" LOC = "AB10" ;
NET "cntrl0_ddr1_dm(8)" LOC = "AH8" ;
NET "cntrl0_ddr1_rasb" LOC = "P3" ;
NET "cntrl0_ddr1_casb" LOC = "T11" ;
NET "cntrl0_ddr1_web" LOC = "U11" ;
NET "cntrl0_ddr1_cke" LOC = "R7" ;
NET "cntrl0_ddr1_csb" LOC = "R6" ;
NET "cntrl0_ddr1_ba(0)" LOC = "U10" ;
NET "cntrl0_ddr1_ba(1)" LOC = "U9" ;
#NET "cntrl0_" LOC = "U6" ;
#NET "cntrl0_" LOC = "Y2" ;
NET "cntrl0_ddr1_address(0)" LOC = "U6" ;
NET "cntrl0_ddr1_address(1)" LOC = "U5" ;
NET "cntrl0_ddr1_address(2)" LOC = "Y2" ;
NET "cntrl0_ddr1_address(3)" LOC = "Y6" ;
NET "cntrl0_ddr1_address(4)" LOC = "Y7" ;
NET "cntrl0_ddr1_address(5)" LOC = "AA2" ;
NET "cntrl0_ddr1_address(6)" LOC = "AB2" ;
NET "cntrl0_ddr1_address(7)" LOC = "AB5" ;
NET "cntrl0_ddr1_address(8)" LOC = "AB6" ;
NET "cntrl0_ddr1_address(9)" LOC = "AD2" ;
NET "cntrl0_ddr1_address(10)" LOC = "AD5" ;
NET "cntrl0_ddr1_address(11)" LOC = "AD6" ;
NET "cntrl0_ddr1_address(12)" LOC = "AH5" ;
NET "reset_in" LOC = "H26" ;
NET "cntrl0_led_error_output1" LOC = "L18" ;
#########################################################################
# MAXDELAY constraints #
#########################################################################
NET "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div" MAXDELAY = 2000ps;
NET "*/ddr1_top0/data_path0/data_read0/fifo*_data_out(*)" MAXDELAY = 2000ps;
NET "*/ddr1_top0/data_path0/data_read0/fifo*_wr_addr(*)" MAXDELAY = 2500ps;
NET "*/ddr1_top0/data_path0/data_read0/fifo*_rd_addr(*)" MAXDELAY = 6000ps;
NET "*/ddr1_top0/data_path0/data_read0/fifo*_wr_en" MAXDELAY = 1500ps;
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