mem_interface_top.ucf

XILINX memory interface generator. XILINX的外部存储器接口。

INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_31_wr_en_inst" LOC = SLICE_X89Y60;
#############################################################
##  constraints for bit ddr1_dqs, 4, location in tile: 2
NET "cntrl0_ddr1_dqs(4)" LOC = V2;
## LUT location constraints for col 0
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay4_col1/one" LOC = SLICE_X90Y58;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay4_col1/one" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay4_col1/two" LOC = SLICE_X90Y59;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay4_col1/two" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay4_col1/three" LOC = SLICE_X90Y59;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay4_col1/three" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay4_col1/four" LOC = SLICE_X91Y58;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay4_col1/four" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay4_col1/five" LOC = SLICE_X91Y58;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay4_col1/five" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay4_col1/six" LOC = SLICE_X91Y59;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay4_col1/six" BEL = G;
## LUT location constraints for col 1
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay4_col0/one" LOC = SLICE_X88Y58;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay4_col0/one" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay4_col0/two" LOC = SLICE_X88Y59;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay4_col0/two" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay4_col0/three" LOC = SLICE_X88Y59;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay4_col0/three" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay4_col0/four" LOC = SLICE_X89Y58;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay4_col0/four" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay4_col0/five" LOC = SLICE_X89Y58;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay4_col0/five" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay4_col0/six" LOC = SLICE_X89Y59;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay4_col0/six" BEL = G;
#############################################################
##  constraints for bit ddr1_dq, 32, location in tile: 1
NET "cntrl0_ddr1_dq(32)" LOC = U4;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit32" LOC = SLICE_X90Y57;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit32" BEL = F;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit32" LOC = SLICE_X88Y57;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit32" BEL = F;
#############################################################
##  constraints for bit ddr1_dq, 33, location in tile: 0
NET "cntrl0_ddr1_dq(33)" LOC = U3;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit33" LOC = SLICE_X90Y57;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit33" BEL = G;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit33" LOC = SLICE_X88Y57;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit33" BEL = G;
#############################################################
##  constraints for bit ddr1_dq, 34, location in tile: 3
NET "cntrl0_ddr1_dq(34)" LOC = V3;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit34" LOC = SLICE_X90Y54;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit34" BEL = F;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit34" LOC = SLICE_X88Y54;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit34" BEL = F;
#############################################################
##  constraints for bit ddr1_dq, 35, location in tile: 2
NET "cntrl0_ddr1_dq(35)" LOC = V4;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit35" LOC = SLICE_X90Y54;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit35" BEL = G;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit35" LOC = SLICE_X88Y54;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit35" BEL = G;
#############################################################
##  constraints for bit ddr1_dq, 36, location in tile: 3
NET "cntrl0_ddr1_dq(36)" LOC = V7;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit36" LOC = SLICE_X90Y52;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit36" BEL = F;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit36" LOC = SLICE_X88Y52;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit36" BEL = F;
#############################################################
##  constraints for bit ddr1_dq, 37, location in tile: 2
NET "cntrl0_ddr1_dq(37)" LOC = V8;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit37" LOC = SLICE_X90Y52;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit37" BEL = G;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit37" LOC = SLICE_X88Y52;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit37" BEL = G;
#############################################################
##  constraints for bit ddr1_dq, 38, location in tile: 1
NET "cntrl0_ddr1_dq(38)" LOC = V5;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit38" LOC = SLICE_X90Y53;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit38" BEL = F;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit38" LOC = SLICE_X88Y53;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit38" BEL = F;
#############################################################
##  constraints for bit ddr1_dq, 39, location in tile: 0
NET "cntrl0_ddr1_dq(39)" LOC = V6;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit39" LOC = SLICE_X90Y53;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit39" BEL = G;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit39" LOC = SLICE_X88Y53;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit39" BEL = G;
#############################################################
##  constraints for bit no_dpin, 4, location in tile: 2
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_40_wr_addr_inst/bit0" LOC = SLICE_X90Y50;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_40_wr_addr_inst/bit1" LOC = SLICE_X90Y50;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_40_wr_addr_inst/bit2" LOC = SLICE_X90Y51;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_40_wr_addr_inst/bit3" LOC = SLICE_X90Y51;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_41_wr_addr_inst/bit0" LOC = SLICE_X88Y50;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_41_wr_addr_inst/bit1" LOC = SLICE_X88Y50;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_41_wr_addr_inst/bit2" LOC = SLICE_X88Y51;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_41_wr_addr_inst/bit3" LOC = SLICE_X88Y51;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_40_wr_en_inst" LOC = SLICE_X91Y50;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_41_wr_en_inst" LOC = SLICE_X89Y50;
#############################################################
##  constraints for bit ddr1_dqs, 5, location in tile: 2
NET "cntrl0_ddr1_dqs(5)" LOC = V10;
## LUT location constraints for col 0
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay5_col1/one" LOC = SLICE_X90Y48;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay5_col1/one" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay5_col1/two" LOC = SLICE_X90Y49;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay5_col1/two" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay5_col1/three" LOC = SLICE_X90Y49;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay5_col1/three" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay5_col1/four" LOC = SLICE_X91Y48;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay5_col1/four" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay5_col1/five" LOC = SLICE_X91Y48;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay5_col1/five" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay5_col1/six" LOC = SLICE_X91Y49;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay5_col1/six" BEL = G;
## LUT location constraints for col 1
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay5_col0/one" LOC = SLICE_X88Y48;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay5_col0/one" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay5_col0/two" LOC = SLICE_X88Y49;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay5_col0/two" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay5_col0/three" LOC = SLICE_X88Y49;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay5_col0/three" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay5_col0/four" LOC = SLICE_X89Y48;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay5_col0/four" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay5_col0/five" LOC = SLICE_X89Y48;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay5_col0/five" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay5_col0/six" LOC = SLICE_X89Y49;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay5_col0/six" BEL = G;
#############################################################
##  constraints for bit ddr1_dq, 40, location in tile: 3
NET "cntrl0_ddr1_dq(40)" LOC = Y1;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit40" LOC = SLICE_X90Y46;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit40" BEL = F;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit40" LOC = SLICE_X88Y46;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit40" BEL = F;
#############################################################
##  constraints for bit ddr1_dq, 41, location in tile: 2
NET "cntrl0_ddr1_dq(41)" LOC = AA1;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit41" LOC = SLICE_X90Y46;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit41" BEL = G;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit41" LOC = SLICE_X88Y46;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit41" BEL = G;
#############################################################
##  constraints for bit ddr1_dq, 42, location in tile: 3
NET "cntrl0_ddr1_dq(42)" LOC = V11;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit42" LOC = SLICE_X90Y44;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit42" BEL = F;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit42" LOC = SLICE_X88Y44;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit42" BEL = F;
#############################################################
##  constraints for bit ddr1_dq, 43, location in tile: 2
NET "cntrl0_ddr1_dq(43)" LOC = W11;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit43" LOC = SLICE_X90Y44;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit43" BEL = G;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit43" LOC = SLICE_X88Y44;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit43" BEL = G;
#############################################################
##  constraints for bit ddr1_dq, 44, location in tile: 1
NET "cntrl0_ddr1_dq(44)" LOC = W5;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit44" LOC = SLICE_X90Y45;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit44" BEL = F;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit44" LOC = SLICE_X88Y45;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit44" BEL = F;
#############################################################
##  constraints for bit ddr1_dq, 45, location in tile: 0
NET "cntrl0_ddr1_dq(45)" LOC = W6;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit45" LOC = SLICE_X90Y45;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit45" BEL = G;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit45" LOC = SLICE_X88Y45;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit45" BEL = G;
#############################################################
##  constraints for bit ddr1_dq, 46, location in tile: 2
NET "cntrl0_ddr1_dq(46)" LOC = Y4;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit46" LOC = SLICE_X90Y42;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit46" BEL = G;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit46" LOC = SLICE_X88Y42;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit46" BEL = G;
#############################################################
##  constraints for bit ddr1_dq, 47, location in tile: 3
NET "cntrl0_ddr1_dq(47)" LOC = W7;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit47" LOC = SLICE_X90Y40;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit47" BEL = G;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit47" LOC = SLICE_X88Y40;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit47" BEL = G;
#############################################################
##  constraints for bit no_dpin, 5, location in tile: 3
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_50_wr_addr_inst/bit0" LOC = SLICE_X90Y38;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_50_wr_addr_inst/bit1" LOC = SLICE_X90Y38;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_50_wr_addr_inst/bit2" LOC = SLICE_X90Y39;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_50_wr_addr_inst/bit3" LOC = SLICE_X90Y39;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_51_wr_addr_inst/bit0" LOC = SLICE_X88Y38;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_51_wr_addr_inst/bit1" LOC = SLICE_X88Y38;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_51_wr_addr_inst/bit2" LOC = SLICE_X88Y39;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_51_wr_addr_inst/bit3" LOC = SLICE_X88Y39;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_50_wr_en_inst" LOC = SLICE_X91Y38;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_51_wr_en_inst" LOC = SLICE_X89Y38;
#############################################################
##  constraints for bit ddr1_dqs, 6, location in tile: 2
NET "cntrl0_ddr1_dqs(6)" LOC = W10;
## LUT location constraints for col 0
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay6_col