mem_interface_top.ucf

XILINX memory interface generator. XILINX的外部存储器接口。

##  constraints for bit no_dpin, 1, location in tile: 1
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_10_wr_addr_inst/bit0" LOC = SLICE_X90Y84;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_10_wr_addr_inst/bit1" LOC = SLICE_X90Y84;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_10_wr_addr_inst/bit2" LOC = SLICE_X90Y85;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_10_wr_addr_inst/bit3" LOC = SLICE_X90Y85;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_11_wr_addr_inst/bit0" LOC = SLICE_X88Y84;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_11_wr_addr_inst/bit1" LOC = SLICE_X88Y84;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_11_wr_addr_inst/bit2" LOC = SLICE_X88Y85;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_11_wr_addr_inst/bit3" LOC = SLICE_X88Y85;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_10_wr_en_inst" LOC = SLICE_X91Y84;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_11_wr_en_inst" LOC = SLICE_X89Y84;
#############################################################
##  constraints for bit ddr1_dqs, 2, location in tile: 2
NET "cntrl0_ddr1_dqs(2)" LOC = N1;
## LUT location constraints for col 0
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col1/one" LOC = SLICE_X90Y82;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col1/one" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col1/two" LOC = SLICE_X90Y83;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col1/two" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col1/three" LOC = SLICE_X90Y83;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col1/three" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col1/four" LOC = SLICE_X91Y82;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col1/four" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col1/five" LOC = SLICE_X91Y82;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col1/five" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col1/six" LOC = SLICE_X91Y83;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col1/six" BEL = G;
## LUT location constraints for col 1
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col0/one" LOC = SLICE_X88Y82;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col0/one" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col0/two" LOC = SLICE_X88Y83;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col0/two" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col0/three" LOC = SLICE_X88Y83;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col0/three" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col0/four" LOC = SLICE_X89Y82;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col0/four" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col0/five" LOC = SLICE_X89Y82;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col0/five" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col0/six" LOC = SLICE_X89Y83;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col0/six" BEL = G;
#############################################################
##  constraints for bit ddr1_dq, 16, location in tile: 1
NET "cntrl0_ddr1_dq(16)" LOC = N4;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit16" LOC = SLICE_X90Y81;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit16" BEL = F;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit16" LOC = SLICE_X88Y81;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit16" BEL = F;
#############################################################
##  constraints for bit ddr1_dq, 17, location in tile: 0
NET "cntrl0_ddr1_dq(17)" LOC = N3;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit17" LOC = SLICE_X90Y81;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit17" BEL = G;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit17" LOC = SLICE_X88Y81;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit17" BEL = G;
#############################################################
##  constraints for bit ddr1_dq, 18, location in tile: 3
NET "cntrl0_ddr1_dq(18)" LOC = N2;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit18" LOC = SLICE_X90Y78;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit18" BEL = F;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit18" LOC = SLICE_X88Y78;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit18" BEL = F;
#############################################################
##  constraints for bit ddr1_dq, 19, location in tile: 2
NET "cntrl0_ddr1_dq(19)" LOC = P2;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit19" LOC = SLICE_X90Y78;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit19" BEL = G;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit19" LOC = SLICE_X88Y78;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit19" BEL = G;
#############################################################
##  constraints for bit ddr1_dq, 20, location in tile: 1
NET "cntrl0_ddr1_dq(20)" LOC = R10;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit20" LOC = SLICE_X90Y79;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit20" BEL = F;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit20" LOC = SLICE_X88Y79;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit20" BEL = F;
#############################################################
##  constraints for bit ddr1_dq, 21, location in tile: 0
NET "cntrl0_ddr1_dq(21)" LOC = R9;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit21" LOC = SLICE_X90Y79;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit21" BEL = G;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit21" LOC = SLICE_X88Y79;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit21" BEL = G;
#############################################################
##  constraints for bit ddr1_dq, 22, location in tile: 1
NET "cntrl0_ddr1_dq(22)" LOC = P6;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit22" LOC = SLICE_X90Y77;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit22" BEL = F;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit22" LOC = SLICE_X88Y77;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit22" BEL = F;
#############################################################
##  constraints for bit ddr1_dq, 23, location in tile: 0
NET "cntrl0_ddr1_dq(23)" LOC = P5;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit23" LOC = SLICE_X90Y77;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit23" BEL = G;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit23" LOC = SLICE_X88Y77;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit23" BEL = G;
#############################################################
##  constraints for bit no_dpin, 2, location in tile: 1
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_20_wr_addr_inst/bit0" LOC = SLICE_X90Y74;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_20_wr_addr_inst/bit1" LOC = SLICE_X90Y74;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_20_wr_addr_inst/bit2" LOC = SLICE_X90Y75;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_20_wr_addr_inst/bit3" LOC = SLICE_X90Y75;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_21_wr_addr_inst/bit0" LOC = SLICE_X88Y74;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_21_wr_addr_inst/bit1" LOC = SLICE_X88Y74;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_21_wr_addr_inst/bit2" LOC = SLICE_X88Y75;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_21_wr_addr_inst/bit3" LOC = SLICE_X88Y75;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_20_wr_en_inst" LOC = SLICE_X91Y74;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_21_wr_en_inst" LOC = SLICE_X89Y74;
#############################################################
##  constraints for bit ddr1_dqs, 3, location in tile: 2
NET "cntrl0_ddr1_dqs(3)" LOC = R1;
## LUT location constraints for col 0
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col1/one" LOC = SLICE_X90Y70;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col1/one" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col1/two" LOC = SLICE_X90Y71;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col1/two" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col1/three" LOC = SLICE_X90Y71;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col1/three" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col1/four" LOC = SLICE_X91Y70;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col1/four" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col1/five" LOC = SLICE_X91Y70;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col1/five" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col1/six" LOC = SLICE_X91Y71;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col1/six" BEL = G;
## LUT location constraints for col 1
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col0/one" LOC = SLICE_X88Y70;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col0/one" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col0/two" LOC = SLICE_X88Y71;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col0/two" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col0/three" LOC = SLICE_X88Y71;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col0/three" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col0/four" LOC = SLICE_X89Y70;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col0/four" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col0/five" LOC = SLICE_X89Y70;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col0/five" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col0/six" LOC = SLICE_X89Y71;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col0/six" BEL = G;
#############################################################
##  constraints for bit ddr1_dq, 24, location in tile: 1
NET "cntrl0_ddr1_dq(24)" LOC = R4;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit24" LOC = SLICE_X90Y69;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit24" BEL = F;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit24" LOC = SLICE_X88Y69;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit24" BEL = F;
#############################################################
##  constraints for bit ddr1_dq, 25, location in tile: 0
NET "cntrl0_ddr1_dq(25)" LOC = R3;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit25" LOC = SLICE_X90Y69;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit25" BEL = G;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit25" LOC = SLICE_X88Y69;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit25" BEL = G;
#############################################################
##  constraints for bit ddr1_dq, 26, location in tile: 2
NET "cntrl0_ddr1_dq(26)" LOC = T2;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit26" LOC = SLICE_X90Y66;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit26" BEL = G;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit26" LOC = SLICE_X88Y66;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit26" BEL = G;
#############################################################
##  constraints for bit ddr1_dq, 27, location in tile: 1
NET "cntrl0_ddr1_dq(27)" LOC = T8;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit27" LOC = SLICE_X90Y67;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit27" BEL = F;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit27" LOC = SLICE_X88Y67;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit27" BEL = F;
#############################################################
##  constraints for bit ddr1_dq, 28, location in tile: 0
NET "cntrl0_ddr1_dq(28)" LOC = T7;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit28" LOC = SLICE_X90Y67;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit28" BEL = G;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit28" LOC = SLICE_X88Y67;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit28" BEL = G;
#############################################################
##  constraints for bit ddr1_dq, 29, location in tile: 1
NET "cntrl0_ddr1_dq(29)" LOC = T6;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit29" LOC = SLICE_X90Y65;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit29" BEL = F;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit29" LOC = SLICE_X88Y65;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit29" BEL = F;
#############################################################
##  constraints for bit ddr1_dq, 30, location in tile: 0
NET "cntrl0_ddr1_dq(30)" LOC = T5;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit30" LOC = SLICE_X90Y65;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit30" BEL = G;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit30" LOC = SLICE_X88Y65;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit30" BEL = G;
#############################################################
##  constraints for bit ddr1_dq, 31, location in tile: 3
NET "cntrl0_ddr1_dq(31)" LOC = T4;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit31" LOC = SLICE_X90Y62;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit31" BEL = G;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit31" LOC = SLICE_X88Y62;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit31" BEL = G;
#############################################################
##  constraints for bit no_dpin, 3, location in tile: 1
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_30_wr_addr_inst/bit0" LOC = SLICE_X90Y60;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_30_wr_addr_inst/bit1" LOC = SLICE_X90Y60;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_30_wr_addr_inst/bit2" LOC = SLICE_X90Y61;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_30_wr_addr_inst/bit3" LOC = SLICE_X90Y61;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_31_wr_addr_inst/bit0" LOC = SLICE_X88Y60;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_31_wr_addr_inst/bit1" LOC = SLICE_X88Y60;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_31_wr_addr_inst/bit2" LOC = SLICE_X88Y61;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_31_wr_addr_inst/bit3" LOC = SLICE_X88Y61;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_30_wr_en_inst" LOC = SLICE_X91Y60;