📄 mem_interface_top.ucf
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INST "infrastructure_top0/cal_top0/tap_dly0/l2" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l3" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l4" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l5" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l6" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l7" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l8" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l9" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l10" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l11" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l12" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l13" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l14" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l15" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l16" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l17" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l18" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l19" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l20" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l21" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l22" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l23" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l24" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l25" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l26" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l27" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l28" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l29" BEL= F;
INST "infrastructure_top0/cal_top0/tap_dly0/l30" BEL= G;
INST "infrastructure_top0/cal_top0/tap_dly0/l31" BEL= F;
#######################################################################################################################
# Area Group Constraint For tap_dly and cal_ctl module #
#######################################################################################################################
INST "infrastructure_top0/cal_top0/cal_ctl0" AREA_GROUP = cal_ctl;
INST "infrastructure_top0/cal_top0/tap_dly0" AREA_GROUP = cal_ctl;
AREA_GROUP "cal_ctl" RANGE = SLICE_X40Y92:SLICE_X49Y101;
AREA_GROUP "cal_ctl" GROUP = CLOSED;
###no_dcm
#######################################################################################################################
# DCM , MACRO and BUFG constraints #
#######################################################################################################################
INST "infrastructure_top0/clk_dcm0/DCM_INST1" LOC="DCM_X3Y0";
INST "infrastructure_top0/clk_dcm0/BUFG_CLK0/u1" LOC="BUFGMUX7S";
INST "infrastructure_top0/clk_dcm0/BUFG_CLK90/u1" LOC="BUFGMUX6P";
NET "infrastructure_top0/clk_dcm0/clk0dcm" MAXDELAY = 0.450ns;
NET "infrastructure_top0/clk_dcm0/clk90dcm" MAXDELAY = 0.450ns;
NET "infrastructure_top0/clk_dcm0/clk0d2inv" MAXDELAY = 0.755ns;
NET "infrastructure_top0/clk_dcm0/clk90d2inv" MAXDELAY = 0.755ns;
#********************************************************************#
# CONTROLLER 0 #
#********************************************************************#
############################################################################
# I/O STANDARDS #
############################################################################
# SSTL2_II for input or output signals
NET "cntrl0_ddr1_dq(*)" IOSTANDARD = SSTL2_II;
NET "cntrl0_ddr1_dqs" IOSTANDARD = SSTL2_II;
NET "cntrl0_ddr1_dm" IOSTANDARD = SSTL2_II;
NET "cntrl0_ddr1_clk*" IOSTANDARD = SSTL2_II;
NET "cntrl0_ddr1_clk*b" IOSTANDARD = SSTL2_II;
NET "cntrl0_ddr1_address(*)" IOSTANDARD = SSTL2_II;
NET "cntrl0_ddr1_ba(*)" IOSTANDARD = SSTL2_II;
NET "cntrl0_ddr1_rasb" IOSTANDARD = SSTL2_II;
NET "cntrl0_ddr1_casb" IOSTANDARD = SSTL2_II;
NET "cntrl0_ddr1_web" IOSTANDARD = SSTL2_II;
NET "cntrl0_ddr1_csb" IOSTANDARD = SSTL2_II;
NET "cntrl0_ddr1_cke" IOSTANDARD = SSTL2_II;
NET "cntrl0_rst_dqs_div_in" IOSTANDARD = SSTL2_II;
NET "cntrl0_rst_dqs_div_out" IOSTANDARD = SSTL2_II;
NET "cntrl0_led_error_output1" IOSTANDARD = LVCMOS25;
############################################################################
# IO Signals Registering Constraints #
############################################################################
INST "*/ddr1_top0/iobs0/datapath_iobs0/ddr_dqs_iob*" IOB = TRUE;
INST "*/ddr1_top0/iobs0/datapath_iobs0/ddr_dq_iob*" IOB = TRUE;
INST "*/ddr1_top0/controller0/rst_iob_out" IOB = TRUE;
INST "*/ddr1_top0/iobs0/controller_iobs0/iob_addr*" IOB = TRUE;
INST "*/ddr1_top0/iobs0/controller_iobs0/iob_ba*" IOB = TRUE;
INST "*/ddr1_top0/iobs0/controller_iobs0/iob_rasb" IOB = TRUE;
INST "*/ddr1_top0/iobs0/controller_iobs0/iob_casb" IOB = TRUE;
INST "*/ddr1_top0/iobs0/controller_iobs0/iob_web" IOB = TRUE;
INST "*/ddr1_top0/iobs0/controller_iobs0/iob_cke" IOB = TRUE;
############################################################################
# Banks 167
# Pin Location Constraints for Clock,Masks, Address, and Controls
############################################################################
NET "cntrl0_led_error_output1" LOC = "L18";
NET "cntrl0_ddr1_clk0" LOC = "G17";
NET "cntrl0_ddr1_clk0b" LOC = "F17";
NET "cntrl0_ddr1_dm" LOC = "G15";
NET "cntrl0_ddr1_ba(0)" LOC = "E10";
NET "cntrl0_ddr1_ba(1)" LOC = "E13";
NET "cntrl0_ddr1_address(0)" LOC = "L16";
NET "cntrl0_ddr1_address(1)" LOC = "C13";
NET "cntrl0_ddr1_address(2)" LOC = "C14";
NET "cntrl0_ddr1_address(3)" LOC = "E14";
NET "cntrl0_ddr1_address(4)" LOC = "F14";
NET "cntrl0_ddr1_address(5)" LOC = "J15";
NET "cntrl0_ddr1_address(6)" LOC = "K15";
NET "cntrl0_ddr1_address(7)" LOC = "C11";
NET "cntrl0_ddr1_address(8)" LOC = "D11";
NET "cntrl0_ddr1_address(9)" LOC = "D12";
NET "cntrl0_ddr1_address(10)" LOC = "D13";
NET "cntrl0_ddr1_address(11)" LOC = "H14";
NET "cntrl0_ddr1_address(12)" LOC = "D10";
##################################################################################
NET "reset_in" LOC = "H26"; # resetN
NET "SYS_CLKb" LOC = "AL18"; # CLK.LVDSP 166Mhz
NET "SYS_CLK" LOC = "AK18"; # CLK.LVDSN 166Mhz
##NET "SYS_CLKb" LOC = "H17"; # CLK.LVDSP 200Mhz
##NET "SYS_CLK" LOC = "J17"; # CLK.LVDSN 200Mhz
NET "cntrl0_ddr1_cke" LOC = "K16";
NET "cntrl0_ddr1_csb" LOC = "F13";
NET "cntrl0_ddr1_rasb" LOC = "C9";
NET "cntrl0_ddr1_casb" LOC = "D9";
NET "cntrl0_ddr1_web" LOC = "G13";
#########################################################################
# MAXDELAY constraints #
#########################################################################
NET "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div" MAXDELAY = 3000ps;
NET "*/ddr1_top0/data_path0/data_read0/fifo*_data_out(*)" MAXDELAY = 2000ps;
NET "*/ddr1_top0/data_path0/data_read0/fifo*_wr_addr(*)" MAXDELAY = 2500ps;
NET "*/ddr1_top0/data_path0/data_read0/fifo*_rd_addr(*)" MAXDELAY = 6000ps;
NET "*/ddr1_top0/data_path0/data_read0/fifo*_wr_en" MAXDELAY = 1500ps;
NET "*/ddr1_top0/data_path0/user_output_data(*)" MAXDELAY = 3000ps;
NET "*/ddr1_top0/controller0/rst_dqs_div_r" MAXDELAY = 1500ps;
#########################################################################
########################################################################
NET "cntrl0_rst_dqs_div_in" LOC = "K12";
NET "cntrl0_rst_dqs_div_out" LOC = "D6";
INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delayed/one" LOC = SLICE_X48Y110;
INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delayed/one" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delayed/two" LOC = SLICE_X48Y111;
INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delayed/two" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delayed/three" LOC = SLICE_X48Y111;
INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delayed/three" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delayed/four" LOC = SLICE_X49Y110;
INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delayed/four" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delayed/five" LOC = SLICE_X49Y110;
INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delayed/five" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delayed/six" LOC = SLICE_X49Y111;
INST "*/ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delayed/six" BEL = G;
#############################################################
## constraints for bit ddr1_dqs, 0, location in tile: 2
NET "cntrl0_ddr1_dqs" LOC = L17;
## LUT location constraints for col 0
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/one" LOC = SLICE_X54Y110;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/one" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/two" LOC = SLICE_X54Y111;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/two" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/three" LOC = SLICE_X54Y111;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/three" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/four" LOC = SLICE_X55Y110;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/four" BEL = F;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/five" LOC = SLICE_X55Y110;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/five" BEL = G;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/six" LOC = SLICE_X55Y111;
INST "*/ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/six" BEL = G;
#############################################################
## constraints for bit ddr1_dq, 0, location in tile: 3
NET "cntrl0_ddr1_dq(0)" LOC = D16;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit0" LOC = SLICE_X56Y110;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit0" BEL = F;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit0" LOC = SLICE_X56Y108;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit0" BEL = F;
#############################################################
## constraints for bit ddr1_dq, 1, location in tile: 2
NET "cntrl0_ddr1_dq(1)" LOC = E16;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit1" LOC = SLICE_X56Y110;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit1" BEL = G;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit1" LOC = SLICE_X56Y108;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit1" BEL = G;
#############################################################
## constraints for bit ddr1_dq, 2, location in tile: 1
NET "cntrl0_ddr1_dq(2)" LOC = F16;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit2" LOC = SLICE_X56Y111;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit2" BEL = G;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit2" LOC = SLICE_X56Y109;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit2" BEL = G;
#############################################################
## constraints for bit ddr1_dq, 3, location in tile: 0
NET "cntrl0_ddr1_dq(3)" LOC = G16;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit3" LOC = SLICE_X56Y111;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit3" BEL = F;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit3" LOC = SLICE_X56Y109;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit3" BEL = F;
#############################################################
## constraints for bit ddr1_dq, 4, location in tile: 2
NET "cntrl0_ddr1_dq(4)" LOC = J16;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit4" LOC = SLICE_X58Y110;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit4" BEL = G;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit4" LOC = SLICE_X58Y108;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit4" BEL = G;
#############################################################
## constraints for bit ddr1_dq, 5, location in tile: 3
NET "cntrl0_ddr1_dq(5)" LOC = D15;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit5" LOC = SLICE_X60Y110;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit5" BEL = F;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit5" LOC = SLICE_X60Y108;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit5" BEL = F;
#############################################################
## constraints for bit ddr1_dq, 6, location in tile: 2
NET "cntrl0_ddr1_dq(6)" LOC = D14;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit6" LOC = SLICE_X60Y110;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit6" BEL = G;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit6" LOC = SLICE_X60Y108;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit6" BEL = G;
#############################################################
## constraints for bit ddr1_dq, 7, location in tile: 1
NET "cntrl0_ddr1_dq(7)" LOC = F15;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_00_wr_addr_inst/bit0" LOC = SLICE_X60Y106;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_00_wr_addr_inst/bit1" LOC = SLICE_X60Y106;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_00_wr_addr_inst/bit2" LOC = SLICE_X60Y107;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_00_wr_addr_inst/bit3" LOC = SLICE_X60Y107;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_01_wr_addr_inst/bit0" LOC = SLICE_X61Y106;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_01_wr_addr_inst/bit1" LOC = SLICE_X61Y106;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_01_wr_addr_inst/bit2" LOC = SLICE_X61Y107;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_01_wr_addr_inst/bit3" LOC = SLICE_X61Y107;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_00_wr_en_inst" LOC = SLICE_X58Y105;
INST "*/ddr1_top0/data_path0/data_read_controller0/fifo_01_wr_en_inst" LOC = SLICE_X60Y105;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit7" LOC = SLICE_X60Y111;
INST "*/ddr1_top0/data_path0/data_read0/fifo0_bit7" BEL = G;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit7" LOC = SLICE_X60Y109;
INST "*/ddr1_top0/data_path0/data_read0/fifo1_bit7" BEL = G;
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