dcmwrapper_2vp7.v

来自「XILINX memory interface generator. XILI」· Verilog 代码 · 共 9 行

`timescale 1ns/100ps
module dcmx1y0_2vp7 (clock1_in, clock2_in, clock1_out, clock2_out); 
   input clock1_in; 
   input clock2_in; 
   output clock1_out;
   output clock2_out; 		
endmodule