cmd_fsm.vhd

XILINX memory interface generator. XILINX的外部存储器接口。

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on
--

entity cmd_fsm is 
port (
      clk          : in std_logic;
      clk180       : in std_logic;
      clk90        : in std_logic;
      cmd_ack      : in std_logic;
      cnt_roll     : in std_logic;
      dip2         : in std_logic;
      dly_tc       : in std_logic;
      r_w          : out std_logic;
      refresh_done : in std_logic;
      rst          : in std_logic;
      rst180       : in std_logic;
      rst90        : in std_logic;
      init_val     : in std_logic;
      u_data_val   : in std_logic;
      addr_inc     : out std_logic;
      addr_rst     : out std_logic;
      u_cmd        : out std_logic_vector(2 downto 0);
--      dly_inc      : out std_logic;
      init_counter : out std_logic_vector(6 downto 0);
      lfsr_rst     : out std_logic;
 auto_ref_req : in std_logic);
     
end cmd_fsm;

architecture arc_cmd_fsm of cmd_fsm is

type s_m is (rst_state, init_start,init, wr, rd, dly, auto_ref_start, auto_ref, rlfsr);--, wait_state, load_mode_wr, lmd_wait_state );
signal next_state, current_state, next_state1 : s_m;

signal init_count     : std_logic;
signal cmd            : std_logic_vector(6 downto 0);
signal cmd_p          : std_logic_vector(6 downto 0);
signal init_dly       : std_logic_vector(5 downto 0);
signal init_dly_p     : std_logic_vector(5 downto 0);
signal init_chek      : std_logic;
signal u_cmd_p        : std_logic_vector(2 downto 0);
signal state_bits     : std_logic_vector(6 downto 0);
signal addr_inc_p     : std_logic;
signal addr_rst_p     : std_logic;
signal dly_inc_p      : std_logic;
signal lfsr_rst_p     : std_logic;
signal lfsr_rst_180   : std_logic;
signal lfsr_rst_90    : std_logic;
signal num_bursts_max : std_logic_vector(3 downto 0);
signal num_burst_done : std_logic_vector(3 downto 0);
signal num_burst      : std_logic_vector(3 downto 0);
signal init_done      : std_logic;
signal r_w1	      : std_logic;
signal r_w2	      : std_logic;
signal next_cmd	      : std_logic;
signal rst_flag	      : std_logic;
signal temp	      : std_logic;
signal clk1 			: std_logic;
signal clk2			: std_logic;
signal clk3 			: std_logic;
signal clk4			: std_logic;

--signal LMD_WAIT_COUNT_value : std_logic_vector(4 downto 0);
--signal LMD_WAIT_COUNT : std_logic_vector(4 downto 0);

begin

clk1 <= clk;
clk2 <= clk1;
clk3 <= clk2;
clk4 <= clk3;

lfsr_rst <= lfsr_rst_90;

init_counter   <= state_bits;
num_bursts_max <= "1111";


--LMD_WAIT_COUNT_value <= "10101" when  (next_state = lmd_wait_state) else
--                        (LMD_WAIT_COUNT - "00001" ) when (LMD_WAIT_COUNT /= "00001")  else 
--                         LMD_WAIT_COUNT;


num_burst_done <= num_bursts_max when (next_state = init_start) else
                  NUM_BURST - "0001" when (next_state = rlfsr) else
                  NUM_BURST;


u_cmd_p <=  "110" when ( next_state = rd ) else			
          "100" when (next_state = wr) else			
          "010" when (next_state = init_start) else		
          "011" when (next_state = auto_ref_start) else		
--        "101" when (next_state = load_mode_wr) else		
          "000";						
          
         
addr_inc_p <= '1' when((cmd_ack = '1') and ((next_state = WR) or (next_state = RD)) ) else
		'0';
              
                     
addr_rst <= rst_flag;

process(clk180)
begin
if(clk180'event and clk180 = '1') then
 rst_flag <= ( not(rst180) and not(cmd_ack) and not(temp));
 temp     <= ( not(rst180) and not(cmd_ack));
end if;
end process;
          

--process(clk)
--begin
--   temp <=  not(cmd_ack) ;
--end process;	      

lfsr_rst_p <= r_w2;

init_dly_p <= "111111" when (next_state = init_start) else
              init_dly - "000001"  when init_dly /= "000000" else
              "000000"; 
              
init_chek  <= init_dly(5) or init_dly(4) or init_dly(3) or init_dly(2) or init_dly(1) or init_dly(0);

----******************************************************************

next_cmd   <= '1' when(cmd_ack = '0' and next_state = dly) else
		'0';
 
process(clk180)
begin
--if(clk180'event and clk180 = '0') then , sarala 5th June
if(clk180'event and clk180 = '1') then
 if(rst180 = '1') then
	r_w1 <= '0';
 else
   if(cmd_ack = '0' and next_state = rd) then--and next_state = dly) then
	r_w1 <= '1';
   elsif(cmd_ack = '0' and next_state = wr) then
        r_w1 <= '0';
    else
	r_w1 <= r_w1;
   end if;
 end if;
 end if;
end process;

r_w2 <= r_w1;
r_w  <= r_w1;
--**********************************************************************

process(clk180)
begin
 if clk180'event and clk180 = '1' then
  if rst180 = '1' then
    lfsr_rst_180  <= '0';
  else
    lfsr_rst_180  <= lfsr_rst_p;
  end if;
 end if;
end process;

process(clk90)
begin
 if clk90'event and clk90 = '1' then
  if rst90 = '1' then
    lfsr_rst_90  <= '0';
  else
    lfsr_rst_90  <= lfsr_rst_180;
  end if;
 end if;
end process;

--for REL6
process(clk180)
begin
 if clk180'event and clk180 = '1' then
  if rst180 = '1' then
      u_cmd <= "000";
  else
      u_cmd <= u_cmd_p;
  end if;
 end if;
end process;   


process(clk180)
begin
 if clk180'event and clk180 = '1' then
  if rst180 = '1' then
--      u_cmd <= "000";
      cmd   <= "0000000";
--      LMD_WAIT_COUNT <= "00000"; 
  else
--      u_cmd <= u_cmd_p;
      cmd   <= cmd_p;
--      LMD_WAIT_COUNT <= LMD_WAIT_COUNT_value;
  end if;
 end if;
end process;             
                           
process(clk180)
begin
 if clk180'event and clk180 = '1' then
   if rst180 = '1' then
       addr_inc  <= '0';
       init_dly  <= "000000";
     else
       addr_inc  <= addr_inc_p;
       init_dly  <= init_dly_p;
     end if;   
    end if;
end process;

process(clk180)
begin
 if clk180'event and clk180 = '1' then
   if rst180 = '1' then
       init_done <= '0';
   else
       init_done <= init_val;
   end if;
 end if;
end process;   

process( rst180, cnt_roll, r_w2, dly_tc, refresh_done, dip2, init_done,next_cmd, next_state)--clk
begin
  if rst180 = '1' then
      next_state1 <= rst_state;
  --elsif clk'event and clk = '1' then
  else
  case(next_state) is
     when rst_state => 
                 if dip2 = '1' then
                    next_state1 <= init_start;
                 else
                    next_state1 <= rst_state;
                 end if;
                 
     when init_start =>
                  next_state1 <= init;
                  
     when init =>
                 if init_done = '1' then
                     next_state1 <= wr;
                 else
                     next_state1 <= init;
                 end if;

      when wr =>
                 if cnt_roll = '0' then
                    next_state1 <= wr;
                 else
                    next_state1 <= dly;
                 end if;
           
     when rlfsr =>
                 --if CTRL_READY = '0' then
                 --   next_state <= rlfsr;
                 --if num_burst = "0001" then
                 --    next_state <= wait_state;
                 
                 if (r_w2 = '0') then
                     next_state1 <= wr;
                 elsif r_w2 = '1' then
                    next_state1 <= rd;
                 end if;
     when dly =>
                 if(next_cmd = '1' and r_w2 = '0') then
			next_state1 <= rd;
		 elsif(next_cmd = '1' and r_w2 = '1') then
			next_state1 <= wr;
		 else
			next_state1 <= dly;
		 end if;
                 
      when auto_ref_start =>
                 next_state1 <= auto_ref;           
                 
      when auto_ref =>
                 if refresh_done = '1' then
                     next_state1 <= rlfsr;
                 else
                     next_state1 <= auto_ref;
                 end if;
      when rd =>
                 if cnt_roll = '0' then
                     next_state1 <= rd;
                 else
                    next_state1 <= dly;
--                     next_state <= lmd_wait_state;
                 end if;
--      when wait_state => 
--                if LMD_WAIT_COUNT = "00001" then
--                   next_state <=dly;
--                else   
--                  next_state <= wait_state;           
--                end if;

--       when lmd_wait_state =>
--                   next_state <= wait_state;

--      when load_mode_wr =>         
--                   next_state <= dly;           
                  
                 
                
      end case;
   end if;
      case next_state is
          when rst_state =>
                state_bits <= "0000001";   -- 01
          when init_start =>
                state_bits <= "0000011";   -- 03
          when init =>
                state_bits <= "0000010";   -- 02
          when wr =>
                state_bits <= "0000100";   -- 04 
          when rlfsr =>
                state_bits <= "0001000";   -- 08
          when dly =>
                state_bits <= "0010000";   -- 10
          when rd =>
                state_bits <= "0100000";   -- 20
         -- when wait_state =>
          --      state_bits <= "1000000";   -- 40  
          when others =>
                state_bits <= "0000000";                                            
      end case;
       
end process;

process(clk180)
begin
 if clk180'event and clk180 = '1' then
  if rst180 = '1' then
    current_state <= rst_state;
    next_state	   <= rst_state;
  else
    next_state    <= next_state1;
    current_state <= next_state;
  end if;
 end if;
end process;


end arc_cmd_fsm;