cmp_data_24bit.vhd

XILINX memory interface generator. XILINX的外部存储器接口。

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on

entity cmp_data_24bit is
port(
     clk            : in std_logic;
     data_valid     : in std_logic;
     lfsr_data      : in std_logic_vector(47 downto 0);
     read_data      : in std_logic_vector(47 downto 0);
     rst            : in std_logic;
     led_error_output : out std_logic;
     data_valid_out : out std_logic
     );
end cmp_data_24bit;

architecture arc_cmp_data_24bit of cmp_data_24bit is

component OBUF 
	port(
	     O    :	out   STD_LOGIC;
	     I    :	in    STD_LOGIC
	     );
	end component;

--type state is (idle, flag_error);
--signal led_state     : state;

signal led_state     : std_logic;
signal valid         : std_logic;
signal error         : std_logic;
signal lfsr_0        : std_logic_vector(15 downto 0);
signal lfsr_1        : std_logic_vector(15 downto 0);
signal lfsr_2        : std_logic_vector(15 downto 0);
signal data_0        : std_logic_vector(15 downto 0);
signal data_1        : std_logic_vector(15 downto 0);
signal data_2        : std_logic_vector(15 downto 0);
signal byte_err      : std_logic_vector(2 downto 0);
signal byte_err1     : std_logic_vector(2 downto 0);
signal valid_1       : std_logic;
signal val_reg       : std_logic;
signal read_data_reg : std_logic_vector(47 downto 0);

begin

process(clk)
begin
 if clk'event and clk = '1' then
  if rst = '1' then
    read_data_reg <= (others => '0');
  else
    read_data_reg <= read_data;
  end if;
 end if;
end process;

process (clk)
begin
 if clk'event and clk ='1' then
  if rst = '1' then
      valid_1 <= '0';
      valid <= '0';
  else
      valid_1 <= data_valid;
      valid <= data_valid;
  end if;
 end if;
end process;       

data_valid_out <= valid;


data_0 <= read_data_reg(15 downto 0);
data_1 <= read_data_reg(31 downto 16);
data_2 <= read_data_reg(47 downto 32);

			
lfsr_0 <= lfsr_data(15 downto 0);
lfsr_1 <= lfsr_data(31 downto 16);
lfsr_2 <= lfsr_data(47 downto 32);


process(clk)
begin
	if clk'event and clk = '1' then
		if (rst='1') then
                        byte_err  <= "000";
                        byte_err1 <= "000";
                        val_reg   <= '0';
		else
                                val_reg  <= valid;
				if (data_0(7 downto 0) /= lfsr_0(7 downto 0)) then
					byte_err(0) <= '1';
				else
					byte_err(0) <= '0';
				end if;
				if (data_1(7 downto 0) /= lfsr_1(7 downto 0)) then
					byte_err(1) <= '1';
				else
					byte_err(1) <= '0';
				end if;
				if (data_2(7 downto 0) /= lfsr_2(7 downto 0)) then
					byte_err(2) <= '1';
				else
					byte_err(2) <= '0';
				end if;
					

				if (data_0(15 downto 8) /= lfsr_0(15 downto 8)) then
					byte_err1(0) <= '1';
				else
					byte_err1(0) <= '0';
				end if;
				if (data_1(15 downto 8) /= lfsr_1(15 downto 8)) then
					byte_err1(1) <= '1';
				else
					byte_err1(1) <= '0';
				end if;
				if (data_2(15 downto 8) /= lfsr_2(15 downto 8)) then
					byte_err1(2) <= '1';
				else
					byte_err1(2) <= '0';
				end if;
		end if;
	end if;
end process;

error <= ( (byte_err(0) or byte_err(1) or byte_err(2)) or
           (byte_err1(0) or byte_err1(1) or byte_err1(2)) )
            and val_reg;



-- LED error output
process(clk)
begin
   if clk'event and clk = '1' then
	led_state <= (not rst and ( error or led_state));
   end if;
end process; 

led_error_output <= '1' when led_state = '1' else
                    '0';
              
	
end arc_cmp_data_24bit;