infrastructure_iobs.vhd

XILINX memory interface generator. XILINX的外部存储器接口。

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on
--
entity infrastructure_iobs is
 port(
      SYS_CLK           : in STD_LOGIC;
      SYS_CLKb          : in STD_LOGIC;    
--XST_REMOVECOMMENT clk180 : in std_logic;
--XST_REMOVECOMMENT clk270 : in std_logic;
      rst_dqs_div_int   : in std_logic;
      rst_dqs_div       : out std_logic;
      rst_dqs_div_in    : in std_logic;
      rst_dqs_div_out   : out std_logic;
      sys_clk_ibuf      : out STD_LOGIC
      );
end infrastructure_iobs;

architecture arc_infrastructure_iobs of infrastructure_iobs is


attribute syn_keep : boolean;
attribute xc_props : string;
  
     
---- Component declarations -----

 component IBUFGDS_LVDS_25     
  port ( I  : in std_logic;     
         IB : in std_logic;    
         O  : out std_logic);   
 end component;

component IBUF_SSTL2_II
port (
       I  : in std_logic;
       O  : out std_logic);
end component;

component OBUF_SSTL2_II
port (
       I  : in std_logic;
       O  : out std_logic);
end component;

begin

----  Component instantiations  ----

--- ***********************************
---  DCI Input buffer for System clock
---   
--- ***********************************

lvds_clk_input : IBUFGDS_LVDS_25 port map ( 
                                           I  => SYS_CLK,      
                                           IB => SYS_CLKb,     
                                           O  => sys_clk_ibuf
                                           );

rst_iob_inbuf  :  IBUF_SSTL2_II port map
                            ( I  => rst_dqs_div_in,
                              O  => rst_dqs_div);
  

                            
rst_iob_outbuf  :  OBUF_SSTL2_II port map
                            ( I  => rst_dqs_div_int,
                              O  => rst_dqs_div_out);


end arc_infrastructure_iobs;