📄 ddr1_test_56bit.vhd
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library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.parameter_56bit.all;
--library synplify;
--use synplify.attributes.all;
--
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on
--
entity ddr1_test_56bit is
port(
dip1 : in STD_LOGIC;
dip2 : in std_logic;
dip3 : in std_logic;
--XST_REMOVECOMMENT clk180 : in std_logic;
--XST_REMOVECOMMENT clk270 : in std_logic;
reset_in : in STD_LOGIC;
rst_dqs_div_in : in std_logic;
rst_dqs_div_out : out std_logic;
ddr1_casb : out STD_LOGIC;
delay_sel_val : in STD_LOGIC_VECTOR(4 downto 0);
clk_int : in std_logic;
wait_200us : in std_logic;
clk90_int : in std_logic;
sys_rst_val : in std_logic;
sys_rst90_val : in std_logic;
sys_rst180_val : in std_logic;
sys_rst270_val : in std_logic;
ddr1_cke : out STD_LOGIC;
ddr1_clk0 : out STD_LOGIC;
ddr1_clk0b : out STD_LOGIC;
ddr1_clk1 : out STD_LOGIC;
ddr1_clk1b : out STD_LOGIC;
ddr1_clk2 : out STD_LOGIC;
ddr1_clk2b : out STD_LOGIC;
ddr1_clk3 : out STD_LOGIC;
ddr1_clk3b : out STD_LOGIC;
ddr1_clk4 : out STD_LOGIC;
ddr1_clk4b : out STD_LOGIC;
ddr1_clk5 : out std_logic;
ddr1_clk5b : out std_logic;
ddr1_clk6 : out std_logic;
ddr1_clk6b : out std_logic;
ddr1_clk7 : out std_logic;
ddr1_clk7b : out std_logic;
ddr1_clk8 : out std_logic;
ddr1_clk8b : out std_logic;
ddr1_clk9 : out std_logic;
ddr1_clk9b : out std_logic;
ddr1_clk10 : out std_logic;
ddr1_clk10b : out std_logic;
ddr1_clk11 : out std_logic;
ddr1_clk11b : out std_logic;
ddr1_clk12 : out std_logic;
ddr1_clk12b : out std_logic;
ddr1_clk13 : out std_logic;
ddr1_clk13b : out std_logic;
ddr1_csb : out STD_LOGIC;
ddr1_rasb : out STD_LOGIC;
ddr1_web : out STD_LOGIC;
ddr1_address : out STD_LOGIC_VECTOR((row_address_p - 1) downto 0);
ddr1_ba : out STD_LOGIC_VECTOR((bank_address_p - 1) downto 0);
ddr1_dm : out STD_LOGIC_VECTOR(((mask_width/2)-1) downto 0);
led_error_output1 : out std_logic;
ddr1_dq : inout STD_LOGIC_VECTOR(55 downto 0);
ddr1_dqs : inout STD_LOGIC_VECTOR(13 downto 0)
);
end ddr1_test_56bit;
architecture arc_ddr1_test_56bit of ddr1_test_56bit is
---- Component declarations -----
component ddr1_test_bench_56bit
port(
dip2 : in std_logic;
--XST_REMOVECOMMENT clk180 : in std_logic;
clk90 : in std_logic;
fpga_clk : in std_logic;
fpga_rst0 : in std_logic;
fpga_rst90 : in std_logic;
fpga_rst180 : in std_logic;
fpga_rst270 : in std_logic;
burst_done : out std_logic;
INIT_DONE : in std_logic;
auto_ref_req : in std_logic;
ar_done : in std_logic;
u_ack : in std_logic;
u_data_val : in std_logic;
u_data_o : in std_logic_vector(111 downto 0);
u_addr : out std_logic_vector(((row_address_p + column_address_p + bank_address_p)-1) downto 0);
u_cmd : out std_logic_vector(2 downto 0);
u_data_i : out std_logic_vector(111 downto 0);
u_data_m : out std_logic_vector(((mask_width)-1) downto 0);
u_config_parms : out std_logic_vector(9 downto 0);
led_error_output : out std_logic;
data_valid_out : out std_logic
);
end component;
component ddr1_top_56bit
port(
dip1 : in std_logic;
dip3 : in std_logic;
--XST_REMOVECOMMENT clk180 : in std_logic;
--XST_REMOVECOMMENT clk270 : in std_logic;
rst_dqs_div_in : in std_logic;
rst_dqs_div_out : out std_logic;
reset_in : in std_logic;
user_input_data : in std_logic_vector(111 downto 0);
user_data_mask : in std_logic_vector(((mask_width)-1) downto 0);
user_output_data : out std_logic_vector(111 downto 0):=(OTHERS => 'Z');
user_data_valid : out std_logic;
user_input_address : in std_logic_vector(((row_address_p + column_address_p)-1) downto 0);
user_bank_address : in std_logic_vector((bank_address_p-1) downto 0);
user_config_register : in std_logic_vector(9 downto 0);
user_command_register : in std_logic_vector(2 downto 0);
user_cmd_ack : out std_logic;
burst_done : in std_logic;
init_val : out std_logic;
auto_ref_req : out std_logic;
ar_done : out std_logic;
ddr_dqs : inout std_logic_vector(13 downto 0);
ddr_dq : inout std_logic_vector(55 downto 0):= (OTHERS => 'Z');
ddr_cke : out std_logic;
ddr_csb : out std_logic;
ddr_rasb : out std_logic;
ddr_casb : out std_logic;
ddr_web : out std_logic;
ddr_dm : out std_logic_vector(((mask_width/2)-1) downto 0);
ddr_ba : out std_logic_vector((bank_address_p-1) downto 0);
ddr_address : out std_logic_vector((row_address_p-1) downto 0);
delay_sel_val : in STD_LOGIC_VECTOR(4 downto 0);
clk_int : in std_logic;
wait_200us : in std_logic;
clk90_int : in std_logic;
sys_rst : in std_logic;
sys_rst90 : in std_logic;
sys_rst180 : in std_logic;
ddr1_clk0 : out std_logic;
ddr1_clk0b : out std_logic;
ddr1_clk1 : out std_logic;
ddr1_clk1b : out std_logic;
ddr1_clk2 : out std_logic;
ddr1_clk2b : out std_logic;
ddr1_clk3 : out std_logic;
ddr1_clk3b : out std_logic;
ddr1_clk4 : out std_logic;
ddr1_clk4b : out std_logic;
ddr1_clk5 : out std_logic;
ddr1_clk5b : out std_logic;
ddr1_clk6 : out std_logic;
ddr1_clk6b : out std_logic;
ddr1_clk7 : out std_logic;
ddr1_clk7b : out std_logic;
ddr1_clk8 : out std_logic;
ddr1_clk8b : out std_logic;
ddr1_clk9 : out std_logic;
ddr1_clk9b : out std_logic;
ddr1_clk10 : out std_logic;
ddr1_clk10b : out std_logic;
ddr1_clk11 : out std_logic;
ddr1_clk11b : out std_logic;
ddr1_clk12 : out std_logic;
ddr1_clk12b : out std_logic;
ddr1_clk13 : out std_logic;
ddr1_clk13b : out std_logic;
sys_rst270 : in std_logic
);
end component;
---- Signal declarations used on the diagram ----
signal user_output_data : std_logic_vector(111 downto 0);
signal u1_address : std_logic_vector(((row_address_p + column_address_p + bank_address_p)-1) downto 0);
signal user_data_val1 : std_logic;
signal u1_config_parms : std_logic_vector(9 downto 0);
signal user_cmd1 : std_logic_vector(2 downto 0);
signal auto_ref_req : std_logic;
signal user_ack1 : std_logic;
signal u1_data_i : std_logic_vector(111 downto 0);
signal u1_data_m : std_logic_vector(((mask_width)-1) downto 0);
signal burst_done_val1 : std_logic;
signal init_val1 : std_logic;
signal pass_val1 : std_logic;
signal ar_done_val1 : std_logic;
signal data_valid_out1 : std_logic;
begin
---- Component instantiations ----
ddr1_top0 : ddr1_top_56bit port map(
auto_ref_req => auto_ref_req,
wait_200us => wait_200us,
dip1 => dip1,
dip3 => dip3,
clk_int => clk_int,
--XST_REMOVECOMMENT clk180 => clk180,
--XST_REMOVECOMMENT clk270 => clk270,
rst_dqs_div_in => rst_dqs_div_in,
rst_dqs_div_out => rst_dqs_div_out,
reset_in => reset_in,
user_input_data => u1_data_i,
user_data_mask => u1_data_m,
user_output_data => user_output_data,
user_data_valid => user_data_val1,
user_input_address => u1_address(((row_address_p + column_address_p + bank_address_p)-1) downto bank_address_p),
user_bank_address => u1_address((bank_address_p-1) downto 0),
user_config_register => u1_config_parms,
user_command_register => user_cmd1,
user_cmd_ack => user_ack1,
burst_done => burst_done_val1,
init_val => init_val1,
ar_done => ar_done_val1,
ddr_dqs => ddr1_dqs,
ddr_dq => ddr1_dq,
ddr_cke => ddr1_cke,
ddr_csb => ddr1_csb,
ddr_rasb => ddr1_rasb,
ddr_casb => ddr1_casb,
ddr_web => ddr1_web,
ddr_dm => ddr1_dm,
ddr_ba => ddr1_ba,
ddr_address => ddr1_address,
ddr1_clk0 => ddr1_clk0,
ddr1_clk0b => ddr1_clk0b,
ddr1_clk1 => ddr1_clk1,
ddr1_clk1b => ddr1_clk1b,
ddr1_clk2 => ddr1_clk2,
ddr1_clk2b => ddr1_clk2b,
ddr1_clk3 => ddr1_clk3,
ddr1_clk3b => ddr1_clk3b,
ddr1_clk4 => ddr1_clk4,
ddr1_clk4b => ddr1_clk4b,
ddr1_clk5 => ddr1_clk5,
ddr1_clk5b => ddr1_clk5b,
ddr1_clk6 => ddr1_clk6,
ddr1_clk6b => ddr1_clk6b,
ddr1_clk7 => ddr1_clk7,
ddr1_clk7b => ddr1_clk7b,
ddr1_clk8 => ddr1_clk8,
ddr1_clk8b => ddr1_clk8b,
ddr1_clk9 => ddr1_clk9,
ddr1_clk9b => ddr1_clk9b,
ddr1_clk10 => ddr1_clk10,
ddr1_clk10b => ddr1_clk10b,
ddr1_clk11 => ddr1_clk11,
ddr1_clk11b => ddr1_clk11b,
ddr1_clk12 => ddr1_clk12,
ddr1_clk12b => ddr1_clk12b,
ddr1_clk13 => ddr1_clk13,
ddr1_clk13b => ddr1_clk13b,
clk90_int => clk90_int,
delay_sel_val => delay_sel_val,
sys_rst => sys_rst_val,
sys_rst90 => sys_rst90_val,
sys_rst180 => sys_rst180_val,
sys_rst270 => sys_rst270_val
);
ddr1_test_bench0 : ddr1_test_bench_56bit port map (
auto_ref_req => auto_ref_req,
fpga_clk => clk_int,
dip2 => dip1 ,
--XST_REMOVECOMMENT clk180 => clk180,
fpga_rst90 => sys_rst90_val,
fpga_rst0 => sys_rst_val,
fpga_rst180 => sys_rst180_val,
fpga_rst270 => sys_rst270_val,
clk90 => clk90_int,
burst_done => burst_done_val1,
INIT_DONE => init_val1,
ar_done => ar_done_val1,
u_ack => user_ack1,
u_data_val => user_data_val1,
u_data_o => user_output_data,
u_addr => u1_address,
u_cmd => user_cmd1,
u_data_i => u1_data_i ,
u_data_m => u1_data_m,
u_config_parms => u1_config_parms,
led_error_output => led_error_output1,
data_valid_out => data_valid_out1
);
end arc_ddr1_test_56bit;
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