lfsr32_32bit.vhd

来自「XILINX memory interface generator. XILI」· VHDL 代码 · 共 55 行

library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--use work.parameter_32bit.all;

entity   lfsr32_32bit  is
  port (
        clk      : in std_logic;
        rst      : in std_logic;
        lfsr_rst : in std_logic;
        lfsr_ena : in std_logic;
	  lfsr_data_m : out std_logic_vector(7 downto 0);
        lfsr_out : out std_logic_vector(63 downto 0));
end   lfsr32_32bit;  

architecture   arc_lfsr32_32bit of   lfsr32_32bit    is

signal lfsr_r : std_logic_vector(7 downto 0);
signal lfsr_f : std_logic_vector(7 downto 0);

attribute syn_preserve : boolean;
attribute syn_preserve of lfsr_r : signal is true;
attribute syn_preserve of lfsr_f : signal is true;

begin

process(clk)
begin
 if rising_edge(clk) then	
  if (rst = '1') then
   lfsr_r <= (others => '0');
   lfsr_f <= "00000001";
  else
   if lfsr_rst = '1' then
     lfsr_r <= (others => '0');
     lfsr_f <= "00000001";
   elsif lfsr_ena = '1' then
     lfsr_r <= lfsr_r + "00000010";        
     lfsr_f <= lfsr_f + "00000010";
   else
     lfsr_r <= lfsr_r;
     lfsr_f <= lfsr_f;
   end if;
  end if;
 end if;
end process;	

lfsr_out <= lfsr_r & lfsr_r & lfsr_r & lfsr_r & 
	    lfsr_f & lfsr_f & lfsr_f & lfsr_f   ;

lfsr_data_m <= (others => '0');

end   arc_lfsr32_32bit;