data_path_rst.v

来自「XILINX memory interface generator. XILI」· Verilog 代码 · 共 44 行

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//--  Xilinx, Inc. 2002                 www.xilinx.com
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//--  File name :       data_path_rst.vhd
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//--  Description :     This module generates the reset signals for data read module
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//--  Date - revision : 10/16/2003
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//--  Author :          Maria George ( Modified by Padmaja Sannala)
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