cal_ctl.v

XILINX memory interface generator. XILINX的外部存储器接口。

			prevSamp <= 1'b0;
		     end else if ((hxSamp1 == 1'b1) && (prevSamp == 1'b1)) begin
			// decrement variable delay
			psEn     <= 1'b1;
			psInc    <= 1'b0;
			state    <= `waitDcmD0;
			prevSamp <= 1'b1;
		     end
 		  end else if (state == `waitDcmD0) begin
		     psEn <= 1'b0;
		     if (psDoneReg) begin
			state <= `idleD0;
		     end
		  end else if (state == `idleD1) begin
		     if ((hxSamp1 == 1'b1) && (prevSamp == 1'b0)) begin
			d1Shft[7:0]  <= zoShft[7:0];
			selTap[4:0]  <= `tap3;
			waitOneCycle <= 1'b1;
			state        <= `idleD2;
			rstate       <= `idleReset;
			resetDcm     <= 1'b1;
		     end else if ((hxSamp1 == 1'b0) && (prevSamp == 1'b1) ) begin
			d1Shft[7:0]  <= ozShft;
			selTap[4:0]  <= `tap3;
			waitOneCycle <= 1'b1;
			state        <= `idleD2;
			rstate       <= `idleReset;
			resetDcm     <= 1'b1;
		     end else if ((hxSamp1 == 1'b0) && (prevSamp == 1'b0)) begin
			// increment phase shift delay
			psEn     <= 1'b1;
			psInc    <= 1'b1;
			state    <= `waitDcmD1;
			prevSamp <= 1'b0;
		     end else if ((hxSamp1 == 1'b1) && (prevSamp == 1'b1)) begin
			// decrement variable delay
			psEn     <= 1'b1;
			psInc    <= 1'b0;
			state    <= `waitDcmD1;
			prevSamp <= 1'b1;
		     end
 		  end else if (state == `waitDcmD1) begin
		     psEn <= 1'b0;
		     if (psDoneReg) begin
			state <= `idleD1;
		     end
	       
		  end else if (state == `idleD2) begin
		     if ((hxSamp1 == 1'b1) && (prevSamp == 1'b0)) begin
			d2Shft[7:0]  <= zoShft[7:0];
			selTap[4:0]  <= `tap4;
			waitOneCycle <= 1'b1;
			state        <= `idleD3;
			rstate       <= `idleReset;
			resetDcm     <= 1'b1;
		     end else if ((hxSamp1 == 1'b0) && (prevSamp == 1'b1) ) begin
			d2Shft[7:0]  <= ozShft[7:0];
			selTap[4:0]  <= `tap4;
			waitOneCycle <= 1'b1;
			state        <= `idleD3;
			rstate       <= `idleReset;
			resetDcm     <= 1'b1;
		     end else if ((hxSamp1 == 1'b0) && (prevSamp == 1'b0)) begin
			// increment phase shift delay
			psEn     <= 1'b1;
			psInc    <= 1'b1;
			state    <= `waitDcmD2;
			prevSamp <= 1'b0;
		     end else if ((hxSamp1 == 1'b1) && (prevSamp == 1'b1)) begin
			// decrement variable delay
			psEn     <= 1'b1;
			psInc    <= 1'b0;
			state    <= `waitDcmD2;
			prevSamp <= 1'b1;
		     end
 		  end else if (state == `waitDcmD2) begin
		     psEn <= 1'b0;
		     if (psDoneReg) begin
			state <= `idleD2;
		     end
		     
		  end else if (state == `idleD3) begin
		     if ((hxSamp1 == 1'b1) && (prevSamp == 1'b0)) begin
			d3Shft[7:0]  <= zoShft[7:0];
			selTap[4:0]  <= `tap5;
			waitOneCycle <= 1'b1;
			state        <= `idleD4;
			rstate       <= `idleReset;
			resetDcm     <= 1'b1;
		     end else if ((hxSamp1 == 1'b0) && (prevSamp == 1'b1) ) begin
			d3Shft[7:0]  <= ozShft[7:0];
			selTap[4:0]  <= `tap5;
			waitOneCycle <= 1'b1;
			state        <= `idleD4;
			rstate       <= `idleReset;
			resetDcm     <= 1'b1;
		     end else if ((hxSamp1 == 1'b0) && (prevSamp == 1'b0)) begin
			// increment phase shift delay
			psEn     <= 1'b1;
			psInc    <= 1'b1;
			state    <= `waitDcmD3;
			prevSamp <= 1'b0;
		     end else if ((hxSamp1 == 1'b1) && (prevSamp == 1'b1)) begin
			// decrement variable delay
			psEn     <= 1'b1;
			psInc    <= 1'b0;
			state    <= `waitDcmD3;
			prevSamp <= 1'b1;
		     end
 		  end else if (state == `waitDcmD3) begin
		     psEn <= 1'b0;
		     if (psDoneReg) begin
			state <= `idleD3;
		     end
		     
		  end else if (state == `idleD4) begin
		     if ((hxSamp1 == 1'b1) && (prevSamp == 1'b0)) begin
			d4Shft[7:0]  <= zoShft[7:0];
			selTap[4:0]  <= `tap6;
			waitOneCycle <= 1'b1;
			state        <= `idleD5;
			rstate       <= `idleReset;
			resetDcm     <= 1'b1;
		     end else if ((hxSamp1 == 1'b0) && (prevSamp == 1'b1) ) begin
			d4Shft[7:0]  <= ozShft[7:0];
			selTap[4:0]  <= `tap6;
			waitOneCycle <= 1'b1;
			state        <= `idleD5;
			rstate       <= `idleReset;
			resetDcm     <= 1'b1;
		     end else if ((hxSamp1 == 1'b0) && (prevSamp == 1'b0)) begin
			// increment phase shift delay
			psEn     <= 1'b1;
			psInc    <= 1'b1;
			state    <= `waitDcmD4;
			prevSamp <= 1'b0;
		     end else if ((hxSamp1 == 1'b1) && (prevSamp == 1'b1)) begin
			// decrement variable delay
			psEn     <= 1'b1;
			psInc    <= 1'b0;
			state    <= `waitDcmD4;
			prevSamp <= 1'b1;
		     end
 		  end else if (state == `waitDcmD4) begin
		     psEn <= 1'b0;
		     if (psDoneReg) begin
			state <= `idleD4;
		     end
		  end else if (state == `idleD5) begin
		     if ((hxSamp1 == 1'b1) && (prevSamp == 1'b0)) begin
			d5Shft[7:0]  <= zoShft[7:0];
			selTap[4:0]  <= `tap1;
			waitOneCycle <= 1'b1;
			state        <= `idleD0;
			rstate       <= `idleReset;
			resetDcm     <= 1'b1;
		     end else if ((hxSamp1 == 1'b0) && (prevSamp == 1'b1) ) begin
			d5Shft[7:0]  <= ozShft[7:0];
			selTap[4:0]  <= `tap1;
			waitOneCycle <= 1'b1;
			state        <= `idleD0;
			rstate       <= `idleReset;
			resetDcm     <= 1'b1;
		     end else if ((hxSamp1 == 1'b0) && (prevSamp == 1'b0)) begin
			// increment phase shift delay
			psEn     <= 1'b1;
			psInc    <= 1'b1;
			state    <= `waitDcmD5;
			prevSamp <= 1'b0;
		     end else if ((hxSamp1 == 1'b1) && (prevSamp == 1'b1)) begin
			// decrement variable delay
			psEn     <= 1'b1;
			psInc    <= 1'b0;
			state    <= `waitDcmD5;
			prevSamp <= 1'b1;
		     end
 		  end else if (state == `waitDcmD5) begin
		     psEn <= 1'b0;
		     if (psDoneReg) begin
			state <= `idleD5;
		     end
		     //end else if (state == `idleDone) begin
		  end
	       end // else: !if(wait4Cycle)
	       
	    end // else: !if(resetDcm)
	    
	       
	    if (psDoneReg && rstate != `waitReset)
	      if (psInc) posPhShft[7:0] <= posPhShft[7:0] + 1'b1;
	      else negPhShft[7:0] <= negPhShft[7:0] + 1'b1;
	    
	 end // if (dcmlocked)
	 
      end // else: !if(reset)
      
   end // always @ (posedge clk)
   
   // Logic to figure out the number of tap delays to use for dqs
   // generate the output tapForDqs

   always @(posedge clk) begin
      if (reset) begin
	 lPtr[2:0] <= 3'b000;
	 uPtr[2:0] <= 3'b101;
	 tapForDqs[4:0] <= `defaultTap;
	 inTapForDqs[4:0] <= `defaultTap;
	 newTap <= `defaultTap;
	 midPt[3:0] <= 4'b0011;
	 okSelCnt <= 1'b0;
      end else begin
	 if (d0Shft[7:0] > `lBound) lPtr[2:0] <= 3'b000;
	 else if (d1Shft[7:0] > `lBound) lPtr[2:0] <= 3'b001;
	 else if (d2Shft[7:0] > `lBound) lPtr[2:0] <= 3'b010;
	 else if (d3Shft[7:0] > `lBound) lPtr[2:0] <= 3'b011;
	 else if (d4Shft[7:0] > `lBound) lPtr[2:0] <= 3'b100;
	 else lPtr[2:0] <= 3'b101;

	 if (d5Shft[7:0] < `uBound) uPtr[2:0] <= 3'b101;
	 else if (d4Shft[7:0] < `uBound) uPtr[2:0] <= 3'b100;
	 else if (d3Shft[7:0] < `uBound) uPtr[2:0] <= 3'b011;
	 else if (d2Shft[7:0] < `uBound) uPtr[2:0] <= 3'b010;
	 else if (d1Shft[7:0] < `uBound) uPtr[2:0] <= 3'b001;
	 else uPtr[2:0] <= 3'b000;

	 midPt[3:0] <= (uPtr[2:0] + lPtr[2:0]) ;
	 	 	 
	 case (midPt[3:1])
	   3'b000: inTapForDqs[4:0] <= `tap1;
	   3'b001: inTapForDqs[4:0] <= `tap2;
	   3'b010: inTapForDqs[4:0] <= `tap3;
	   3'b011: inTapForDqs[4:0] <= `tap4;
	   3'b100: inTapForDqs[4:0] <= `tap5;
	   3'b101: inTapForDqs[4:0] <= `tap6;
	   default: inTapForDqs[4:0] <= inTapForDqs[4:0];
	 endcase // case(midPt[2:0])

	 // tap output shouldn't change unless the same tap value is selected n number of times.
	 newTap[4:0] <= inTapForDqs[4:0];
	 if (inTapForDqs[4:0] == newTap[4:0]) begin
	    
	    if (wait4Cycle) selCnt[3:0] <= selCnt[3:0] + 1'b1;
	    if (selCnt[3:0] == `slipCnt) okSelCnt <= 1'b1;
	    else okSelCnt <= 1'b0;
	 end else begin
	    selCnt[3:0] <= 4'b0000;
	    okSelCnt <= 1'b0;
	 end
	    	 
	 if (okToSelTap && okSelCnt) tapForDqs[4:0] <= newTap[4:0];
	 
      end // else: !if(reset)
   end // always @ (posedge clk)
   
endmodule // cal_ctl