iobs.v

XILINX memory interface generator. XILINX的外部存储器接口。

`timescale 1ns/100ps
`include "parameters_56bit.v" 

module iobs(
                    //inputs
                    SYS_CLK,           
                    SYS_CLKb,          
                    clk,               
                    clk90, 
//XST_REMOVECOMMENT       clk180,
//XST_REMOVECOMMENT       clk270,              
                    ddr_rasb_cntrl,    
                    ddr_casb_cntrl,    
                    ddr_web_cntrl,     
                    ddr_cke_cntrl,     
                    ddr_csb_cntrl,     
                    ddr_address_cntrl, 
                    ddr_ba_cntrl,      
                    rst_dqs_div_int,   
                    dqs_reset,         
                    dqs_enable,        
                    ddr_dqs,           
                    ddr_dq,            
                    write_data_falling,
                    write_data_rising, 
                    write_en_val,      
                    reset270_r,        
                    data_mask_f,       
                    data_mask_r,       
                    //outputs
                    sys_clk_ibuf,      
                    ddr1_clk0,         
                    ddr1_clk0b,        
                    ddr1_clk1,         
                    ddr1_clk1b,        
                    ddr1_clk2,         
                    ddr1_clk2b,        
                    ddr1_clk3,         
                    ddr1_clk3b,        
                    ddr_rasb,          
                    ddr_casb,          
                    ddr_web,           
                    ddr_ba,            
                    ddr_address,       
                    ddr_cke,           
                    ddr_csb,           
                    rst_dqs_div,       
                    rst_dqs_div_in,   
                    rst_dqs_div_out,  
                    dqs_int_delay_in0, 
                    dqs_int_delay_in1, 
                    dqs_int_delay_in2, 
                    dqs_int_delay_in3, 
                    dqs_int_delay_in4, 
                    dqs_int_delay_in5, 
                    dqs_int_delay_in6, 
                     
                    dq,                
                    ddr_dm                         
                   );
           
//input/output declarations

input        SYS_CLK;           
input        SYS_CLKb;          
input        clk;               
input        clk90;   
//XST_REMOVECOMMENT    input   clk180;
//XST_REMOVECOMMENT    input   clk270;            
input        ddr_rasb_cntrl;    
input        ddr_casb_cntrl;    
input        ddr_web_cntrl;     
input        ddr_cke_cntrl;     
input        ddr_csb_cntrl;     
input [12:0] ddr_address_cntrl; 
input [1:0]  ddr_ba_cntrl;      
input        rst_dqs_div_int;   
input        dqs_reset;         
input        dqs_enable;        
inout [6:0]  ddr_dqs;           
inout [55:0] ddr_dq;           
input [55:0] write_data_falling;
input [55:0] write_data_rising; 
input        write_en_val;      
input        reset270_r;        
input [6:0]  data_mask_f;       
input [6:0]  data_mask_r;       
output       sys_clk_ibuf;      
output       ddr1_clk0;         
output       ddr1_clk0b;        
output       ddr1_clk1;         
output       ddr1_clk1b;        
output       ddr1_clk2;         
output       ddr1_clk2b;        
output       ddr1_clk3;         
output       ddr1_clk3b;
output       ddr_rasb;          
output       ddr_casb;          
output       ddr_web;           
output [1:0] ddr_ba;            
output [12:0]ddr_address;       
output       ddr_cke;           
output       ddr_csb;           
output       rst_dqs_div;       
input        rst_dqs_div_in;   
output       rst_dqs_div_out;  
output       dqs_int_delay_in0; 
output       dqs_int_delay_in1; 
output       dqs_int_delay_in2; 
output       dqs_int_delay_in3; 
output       dqs_int_delay_in4; 
output       dqs_int_delay_in5; 
output       dqs_int_delay_in6; 
 
 
output[55:0] dq;                
output[6:0]  ddr_dm;	           
 	           
// modules instantiations

infrastructure_iobs infrastructure_iobs0 (
                                           .SYS_CLK(SYS_CLK),
                                           .SYS_CLKb(SYS_CLKb),
                                           .clk0(clk),
                                           .clk90(clk90),
//XST_REMOVECOMMENT   	.clk180(clk180),
//XST_REMOVECOMMENT   	.clk270(clk270),
                                           .sys_clk_ibuf(sys_clk_ibuf),
                                           .ddr1_clk0(ddr1_clk0),
                                           .ddr1_clk0b(ddr1_clk0b),
                                           .ddr1_clk1(ddr1_clk1),
                                           .ddr1_clk1b(ddr1_clk1b),
                                           .ddr1_clk2(ddr1_clk2),
                                           .ddr1_clk2b(ddr1_clk2b),
                                           .ddr1_clk3(ddr1_clk3),
                                           .ddr1_clk3b(ddr1_clk3b)
                                          );

controller_iobs controller_iobs0 (
                                  .clk0(clk),
//XST_REMOVECOMMENT   	.clk180(clk180),
                                  .ddr_rasb_cntrl(ddr_rasb_cntrl),
                                  .ddr_casb_cntrl(ddr_casb_cntrl),
                                  .ddr_web_cntrl(ddr_web_cntrl), 
                                  .ddr_cke_cntrl(ddr_cke_cntrl),
                                  .ddr_csb_cntrl(ddr_csb_cntrl),
                                  .ddr_address_cntrl(ddr_address_cntrl[12:0]),
                                  .ddr_ba_cntrl(ddr_ba_cntrl[1:0]),
                                  .rst_dqs_div_int(rst_dqs_div_int),
                                  .ddr_rasb(ddr_rasb),
                                  .ddr_casb(ddr_casb),
                                  .ddr_web(ddr_web),
                                  .ddr_ba(ddr_ba[1:0]),
                                  .ddr_address(ddr_address[12:0]),
                                  .ddr_cke(ddr_cke),
                                  .ddr_csb(ddr_csb), 
                                  .rst_dqs_div(rst_dqs_div),
                                  .rst_dqs_div_in(rst_dqs_div_in),
      				  .rst_dqs_div_out(rst_dqs_div_out)
                                 );

data_path_iobs_56bit data_path_iobs0 (
                              .clk(clk),
//XST_REMOVECOMMENT   	.clk180(clk180),
//XST_REMOVECOMMENT   	.clk270(clk270),
                              .dqs_reset(dqs_reset),
                              .dqs_enable(dqs_enable),
                              .ddr_dqs(ddr_dqs),
                              .ddr_dq(ddr_dq),
                              .write_data_falling(write_data_falling[55:0]),
                              .write_data_rising(write_data_rising[55:0]),
                              .write_en_val(write_en_val),
                              .clk90(clk90),
                              .reset270_r(reset270_r),
                              .data_mask_f(data_mask_f[6:0]),
                              .data_mask_r(data_mask_r[6:0]),
                              .dqs_int_delay_in0(dqs_int_delay_in0),
                              .dqs_int_delay_in1(dqs_int_delay_in1),
                              .dqs_int_delay_in2(dqs_int_delay_in2),
                              .dqs_int_delay_in3(dqs_int_delay_in3),
                              .dqs_int_delay_in4(dqs_int_delay_in4),
                              .dqs_int_delay_in5(dqs_int_delay_in5),
                              .dqs_int_delay_in6(dqs_int_delay_in6),
  
                              .dq(dq[55:0]),
                              .ddr_dm(ddr_dm[6:0])
                          );

   
	           
	           
 
 endmodule