iobs.v

XILINX memory interface generator. XILINX的外部存储器接口。

`timescale 1ns/100ps
`include "parameters_64bit.v" 

module iobs(
                    //inputs
                    SYS_CLK,           
                    SYS_CLKb,          
                    clk,               
                    clk90,  
//XST_REMOVECOMMENT       clk180,
//XST_REMOVECOMMENT       clk270,             
                    rst_dqs_div_int,   
                    dqs_reset,         
                    dqs_enable,        
                    ddr_dqs,           
                    ddr_dq,            
                    write_data_falling,
                    write_data_rising, 
                    write_en_val,      
                    reset270_r,        
                    data_mask_f,       
                    data_mask_r,       
                    //outputs
                    sys_clk_ibuf,      
                    rst_dqs_div,       
                    rst_dqs_div_in,   
                    rst_dqs_div_out,  
                    dqs_int_delay_in0, 
                    dqs_int_delay_in1, 
                    dqs_int_delay_in2, 
                    dqs_int_delay_in3, 
                    dqs_int_delay_in4, 
                    dqs_int_delay_in5, 
                    dqs_int_delay_in6, 
                    dqs_int_delay_in7, 
                    dq,                
                    ddr_dm                         
                   );
           
//input/output declarations

input        SYS_CLK;           
input        SYS_CLKb;          
input        clk;               
input        clk90;    
//XST_REMOVECOMMENT    input   clk180;
//XST_REMOVECOMMENT    input   clk270;           
input        rst_dqs_div_int;   
input        dqs_reset;         
input        dqs_enable;        
inout [7:0]  ddr_dqs;           
inout [63:0] ddr_dq;           
input [63:0] write_data_falling;
input [63:0] write_data_rising; 
input        write_en_val;      
input        reset270_r;        
input [7:0]  data_mask_f;       
input [7:0]  data_mask_r;       
output       sys_clk_ibuf;      
output       rst_dqs_div;       
input        rst_dqs_div_in;   
output       rst_dqs_div_out;  
output       dqs_int_delay_in0; 
output       dqs_int_delay_in1; 
output       dqs_int_delay_in2; 
output       dqs_int_delay_in3; 
output       dqs_int_delay_in4; 
output       dqs_int_delay_in5; 
output       dqs_int_delay_in6; 
output       dqs_int_delay_in7; 
output[63:0] dq;                
output[7:0]  ddr_dm;	           
 	           
// modules instantiations

infrastructure_iobs infrastructure_iobs0 (
                                           .SYS_CLK(SYS_CLK),
                                           .SYS_CLKb(SYS_CLKb),
//XST_REMOVECOMMENT   	.clk180(clk180),
//XST_REMOVECOMMENT   	.clk270(clk270),
                       	                   .rst_dqs_div_int(rst_dqs_div_int),
		 	                   .rst_dqs_div_in(rst_dqs_div_in),
		 	                   .sys_clk_ibuf(sys_clk_ibuf),
			                   .rst_dqs_div(rst_dqs_div),      
 			                   .rst_dqs_div_out(rst_dqs_div_out) 
		 	                    
                                         );


data_path_iobs_64bit data_path_iobs0 (
                              .clk(clk),
//XST_REMOVECOMMENT   	.clk180(clk180),
//XST_REMOVECOMMENT   	.clk270(clk270),
                              .dqs_reset(dqs_reset),
                              .dqs_enable(dqs_enable),
                              .ddr_dqs(ddr_dqs),
                              .ddr_dq(ddr_dq),
                              .write_data_falling(write_data_falling[63:0]),
                              .write_data_rising(write_data_rising[63:0]),
                              .write_en_val(write_en_val),
                              .clk90(clk90),
                              .reset270_r(reset270_r),
                              .data_mask_f(data_mask_f[7:0]),
                              .data_mask_r(data_mask_r[7:0]),
                              .dqs_int_delay_in0(dqs_int_delay_in0),
                              .dqs_int_delay_in1(dqs_int_delay_in1),
                              .dqs_int_delay_in2(dqs_int_delay_in2),
                              .dqs_int_delay_in3(dqs_int_delay_in3),
                              .dqs_int_delay_in4(dqs_int_delay_in4),
                              .dqs_int_delay_in5(dqs_int_delay_in5),
                              .dqs_int_delay_in6(dqs_int_delay_in6),
                              .dqs_int_delay_in7(dqs_int_delay_in7),
                              .dq(dq[63:0]),
                              .ddr_dm(ddr_dm[7:0])
                          );

   
	           
	           
 
 endmodule