infrastructure_iobs.v

XILINX memory interface generator. XILINX的外部存储器接口。

`timescale 1ns/100ps

module infrastructure_iobs(
                            //inputs
                            SYS_CLK,           
                            SYS_CLKb,          
                            clk0,              
                            clk90,             
//XST_REMOVECOMMENT       clk180,
//XST_REMOVECOMMENT       clk270,
                            //outputs 
                            sys_clk_ibuf,      
                            ddr1_clk0,         
                            ddr1_clk0b,        
                            ddr1_clk1,         
                            ddr1_clk1b,        
                            ddr1_clk2,         
                            ddr1_clk2b,        
                            ddr1_clk3,         
                            ddr1_clk3b,        
                            ddr1_clk4,         
                            ddr1_clk4b
                           );

//input/output declarations
input       SYS_CLK;           
input       SYS_CLKb;          
input       clk0;              
input       clk90;             
//XST_REMOVECOMMENT    input   clk180;
//XST_REMOVECOMMENT    input   clk270;
output      sys_clk_ibuf;      
output      ddr1_clk0;         
output      ddr1_clk0b;        
output      ddr1_clk1;         
output      ddr1_clk1b;        
output      ddr1_clk2;         
output      ddr1_clk2b;        
output      ddr1_clk3;         
output      ddr1_clk3b;        
output      ddr1_clk4;         
output      ddr1_clk4b;        


//*******************************
//  Internal Wire declarations 
//*******************************

wire   ddr1_clk0_q;          
wire   ddr1_clk0b_q;         
wire   ddr1_clk1_q;          
wire   ddr1_clk1b_q;         
wire   ddr1_clk2_q;          
wire   ddr1_clk2b_q;         
wire   ddr1_clk3_q;          
wire   ddr1_clk3b_q;         
wire   ddr1_clk4_q;          
wire   ddr1_clk4b_q;         
wire   vcc;                  
wire   gnd;                  
//SYN_REMOVECOMMENT wire   clk180;               
//SYN_REMOVECOMMENT wire   clk270;


assign  vcc    =  1'b1;
assign  gnd    =  1'b0;
//SYN_REMOVECOMMENT assign  clk180 =  ~clk0;
//SYN_REMOVECOMMENT assign  clk270 =  ~clk90;


//##### Component instantiations #####

//**************************************
//  DCI Input buffer for System clock
//**************************************

IBUFGDS_LVDS_25  lvds_clk_input( 
                                 .I(SYS_CLK),      
                                 .IB(SYS_CLKb),     
                                 .O(sys_clk_ibuf)
                               );

// ***********************************************************
//     Output DDR generation
//     This includes instantiation of the output DDR flip flop
//     for ddr clk's 
// ***********************************************************

FDDRRSE  U1 (
             .Q(ddr1_clk0_q),
             .C0(clk0),
             .C1(clk180),
             .CE(vcc),
             .D0(vcc),
             .D1(gnd),
             .R(gnd),
             .S(gnd)
            );

FDDRRSE  U2 (
             .Q(ddr1_clk0b_q),
             .C0(clk0),
             .C1(clk180),
             .CE(vcc),
             .D0(gnd),
             .D1(vcc),
             .R(gnd),
             .S(gnd)
            );

FDDRRSE  U3 (
             .Q(ddr1_clk1_q),
             .C0(clk0),
             .C1(clk180),
             .CE(vcc),
             .D0(vcc),
             .D1(gnd),
             .R(gnd),
             .S(gnd)
            );

FDDRRSE  U4 (
             .Q(ddr1_clk1b_q),
             .C0(clk0),
             .C1(clk180),
             .CE(vcc),
             .D0(gnd),
             .D1(vcc),
             .R(gnd),
             .S(gnd)
            );

FDDRRSE  U5 (
             .Q(ddr1_clk2_q),
             .C0(clk0),
             .C1(clk180),
             .CE(vcc),
             .D0(vcc),
             .D1(gnd),
             .R(gnd),
             .S(gnd)
            );

FDDRRSE  U6 (
             .Q(ddr1_clk2b_q),
             .C0(clk0),
             .C1(clk180),
             .CE(vcc),
             .D0(gnd),
             .D1(vcc),
             .R(gnd),
             .S(gnd)
            );

FDDRRSE  U7 (
             .Q(ddr1_clk3_q),
             .C0(clk0),
             .C1(clk180),
             .CE(vcc),
             .D0(vcc),
             .D1(gnd),
             .R(gnd),
             .S(gnd)
            );

FDDRRSE  U8 (
             .Q(ddr1_clk3b_q),
             .C0(clk0),
             .C1(clk180),
             .CE(vcc),
             .D0(gnd),
             .D1(vcc),
             .R(gnd),
             .S(gnd)
            );

FDDRRSE  U9 (
             .Q(ddr1_clk4_q),
             .C0(clk0),
             .C1(clk180),
             .CE(vcc),
             .D0(vcc),
             .D1(gnd),
             .R(gnd),
             .S(gnd)
            );
            

FDDRRSE  U10 (
              .Q(ddr1_clk4b_q),
              .C0(clk0),
              .C1(clk180),
              .CE(vcc),
              .D0(gnd),
              .D1(vcc),
              .R(gnd),
              .S(gnd)
             );


// ******************************
//   Ouput BUffers for ddr clk's 
// ******************************


OBUF r1 (
         .I(ddr1_clk0_q),
         .O(ddr1_clk0)
         );


OBUF r2 (
         .I(ddr1_clk0b_q),
         .O(ddr1_clk0b)
         );

OBUF r3 (
         .I(ddr1_clk1_q),
         .O(ddr1_clk1)
         );

OBUF r4 (
         .I(ddr1_clk1b_q),
         .O(ddr1_clk1b)
         );         


OBUF r5 (
         .I(ddr1_clk2_q),
         .O(ddr1_clk2)
         );
         
OBUF r6 (
         .I(ddr1_clk2b_q),
         .O(ddr1_clk2b)
         );


OBUF r7 (
         .I(ddr1_clk3_q),
         .O(ddr1_clk3)
         );
         
OBUF r8 (
         .I(ddr1_clk3b_q),
         .O(ddr1_clk3b)
         );         


OBUF r9 (
         .I(ddr1_clk4_q),
         .O(ddr1_clk4)
         );

OBUF r10(
         .I(ddr1_clk4b_q),
         .O(ddr1_clk4b)
         );





 endmodule