ddr1_test_40bit.v

XILINX memory interface generator. XILINX的外部存储器接口。

`timescale 1ns/100ps 
`include "parameters_40bit.v"
module    ddr1_test_40bit    
     (
       dip1,              
       dip2,              
       dip3,              
//XST_REMOVECOMMENT clk180,
//XST_REMOVECOMMENT clk270,
       reset_in,          
       clk_int,
       clk90_int,
       delay_sel_val,
       sys_rst_val,
       sys_rst90_val,
       sys_rst180_val,
       sys_rst270_val,
       rst_dqs_div_in,
       rst_dqs_div_out,
       led_error_output1,   
       ddr1_casb,         
       ddr1_cke,          
       ddr1_clk0,         
       ddr1_clk0b,        
       ddr1_clk1,         
       ddr1_clk1b,        
       ddr1_clk2,         
       ddr1_clk2b,        
       ddr1_csb,          
       ddr1_rasb,         
       ddr1_web,          
       ddr1_address,      
       ddr1_ba,           
ddr1_dm,           
       ddr1_dq,          
wait_200us, 
       ddr1_dqs
  );

//Input/Output declarations
input       dip1;              
input       dip2;              
input       dip3;              
//XST_REMOVECOMMENT input clk180;
//XST_REMOVECOMMENT input clk270;
input       clk_int;
input       clk90_int;
input    [4:0] delay_sel_val;
input       sys_rst_val;
input       sys_rst90_val;
input       sys_rst180_val;
input       sys_rst270_val;
input       reset_in;
input       rst_dqs_div_in;    

output      rst_dqs_div_out; 
output      led_error_output1;

output       ddr1_casb;         
output       ddr1_cke;          
output       ddr1_clk0;         
output       ddr1_clk0b;        
output       ddr1_clk1;         
output       ddr1_clk1b;        
output       ddr1_clk2;         
output       ddr1_clk2b;        
output       ddr1_csb;          
output       ddr1_rasb;         
output       ddr1_web;          
output[`row_address-1:0]ddr1_address;     
output [`bank_address-1:0]ddr1_ba;  
output [((`mask_width/2)-1):0]  ddr1_dm;           
inout [39:0]ddr1_dq;      
 input    wait_200us; 
inout  [4:0]ddr1_dqs;         

//internal signal declarations  
wire [79:0] user_output_data; 
wire [((`row_address + `column_address + `bank_address)-1):0] u1_address; 
wire        user_data_val1;         
wire [9:0]  u1_config_parms;         
wire [2:0]  user_cmd1;               
 wire auto_ref_req; 
wire        user_ack1;              
wire [79:0] u1_data_i;   
wire [((`mask_width)-1):0] u1_data_m;           
wire        burst_done_val1;       
wire [79:0] lfsr_out_data1;         
wire [79:0] read_out_data1;     

wire init_val1;               
wire pass_val1;               
wire ar_done_val1;            
wire clk_int;                 
wire clk90_int;               
wire sys_rst;                 
wire sys_rst90;               
wire sys_rst180;              
wire sys_rst270;              
wire data_valid_out1;         

//----  Component instantiations  ----
                                           
ddr1_top_40bit	ddr1_top0( 
.auto_ref_req      (auto_ref_req), 
.wait_200us(wait_200us), 
                               .dip1(dip1),
                               .dip3(dip3),
			//XST_REMOVECOMMENT .clk180(clk180),
			//XST_REMOVECOMMENT .clk270(clk270),
                               .rst_dqs_div_in(rst_dqs_div_in),
                               .rst_dqs_div_out(rst_dqs_div_out),
                               .reset_in(reset_in),
                               .user_input_data(u1_data_i),
					 .user_data_mask(u1_data_m),
                               .user_output_data(user_output_data),
                               .user_data_valid(user_data_val1),
                               .user_input_address(u1_address[((`row_address + `column_address + `bank_address)-1):`bank_address]),
                               .user_bank_address(u1_address[`bank_address-1:0]),
                               .user_config_register(u1_config_parms),
                               .user_command_register(user_cmd1),
                               .user_cmd_ack(user_ack1),
                               .burst_done(burst_done_val1),
                               .init_val(init_val1),
                               .ar_done(ar_done_val1),
                               .ddr_dqs(ddr1_dqs),
                               .ddr_dq (ddr1_dq),
                               .ddr_cke(ddr1_cke),
                               .ddr_csb(ddr1_csb),
                               .ddr_rasb(ddr1_rasb),
                               .ddr_casb(ddr1_casb),
                               .ddr_web(ddr1_web),
.ddr_dm (ddr1_dm),
                               .ddr_ba (ddr1_ba),
                               .ddr_address(ddr1_address),
                               .ddr1_clk0(ddr1_clk0),
                               .ddr1_clk0b(ddr1_clk0b),
                               .ddr1_clk1(ddr1_clk1),
                               .ddr1_clk1b(ddr1_clk1b),
                               .ddr1_clk2(ddr1_clk2),
                               .ddr1_clk2b(ddr1_clk2b),
	.clk_int(clk_int),
	.clk90_int(clk90_int),
	.delay_sel_val(delay_sel_val),
	.sys_rst(sys_rst_val),
	.sys_rst90(sys_rst90_val),
	.sys_rst180(sys_rst180_val),
	.sys_rst270(sys_rst270_val)
                               );                                            

ddr1_test_bench_40bit    ddr1_test_bench0   ( 
 .auto_ref_req      (auto_ref_req),  
                                             .dip2(dip1),
			//XST_REMOVECOMMENT .clk180(clk180),
                                             .fpga_clk(clk_int),
				 .fpga_rst90(sys_rst90_val), 
				 .fpga_rst0(sys_rst_val), 
				 .fpga_rst180(sys_rst180_val), 
				 .fpga_rst270(sys_rst270_val), 
                                             .clk90(clk90_int),
                                             .burst_done(burst_done_val1),
                                             .INIT_DONE(init_val1),
                                             .ar_done(ar_done_val1),
                                             .u_ack(user_ack1),
                                             .u_data_val(user_data_val1),
                                             .u_data_o(user_output_data),
                                             .u_addr(u1_address),
                                             .u_cmd(user_cmd1), 
                                             .u_data_i(u1_data_i),
							   .u_data_m(u1_data_m),
                                             .u_config_parms(u1_config_parms),
                                             .led_error_output(led_error_output1),
                                             .data_valid_out(data_valid_out1),
                                             .state()
                                            );
                                   

endmodule