data_path_iobs_32bit.v

XILINX memory interface generator. XILINX的外部存储器接口。

                            .write_en_val(write_en_val),
                            .reset(reset270_r)
                           ); 
                           
ddr_dq_iob  ddr_dq_iob13( 
                            .ddr_dq_inout(ddr_dq[13]),
                            .write_data_rising(write_data_rising[13]),
                            .write_data_falling(write_data_falling[13]),
                            .read_data_in(dq[13]),
                            .clk90(clk90),
			//XST_REMOVECOMMENT .clk270(clk270),
                            .write_en_val(write_en_val),
                            .reset(reset270_r)
                           ); 
                           
ddr_dq_iob  ddr_dq_iob14( 
                            .ddr_dq_inout(ddr_dq[14]),
                            .write_data_rising(write_data_rising[14]),
                            .write_data_falling(write_data_falling[14]),
                            .read_data_in(dq[14]),
                            .clk90(clk90),
			//XST_REMOVECOMMENT .clk270(clk270),
                            .write_en_val(write_en_val),
                            .reset(reset270_r)
                           ); 
                          
ddr_dq_iob  ddr_dq_iob15( 
                            .ddr_dq_inout(ddr_dq[15]),
                            .write_data_rising(write_data_rising[15]),
                            .write_data_falling(write_data_falling[15]),
                            .read_data_in(dq[15]),
                            .clk90(clk90),
			//XST_REMOVECOMMENT .clk270(clk270),
                            .write_en_val(write_en_val),
                            .reset(reset270_r)
                           ); 
                        
ddr_dq_iob  ddr_dq_iob16( 
                            .ddr_dq_inout(ddr_dq[16]),
                            .write_data_rising(write_data_rising[16]),
                            .write_data_falling(write_data_falling[16]),
                            .read_data_in(dq[16]),
                            .clk90(clk90),
			//XST_REMOVECOMMENT .clk270(clk270),
                            .write_en_val(write_en_val),
                            .reset(reset270_r)
                           ); 
                           
ddr_dq_iob  ddr_dq_iob17( 
                            .ddr_dq_inout(ddr_dq[17]),
                            .write_data_rising(write_data_rising[17]),
                            .write_data_falling(write_data_falling[17]),
                            .read_data_in(dq[17]),
                            .clk90(clk90),
			//XST_REMOVECOMMENT .clk270(clk270),
                            .write_en_val(write_en_val),
                            .reset(reset270_r)
                           ); 
                           
ddr_dq_iob  ddr_dq_iob18( 
                            .ddr_dq_inout(ddr_dq[18]),
                            .write_data_rising(write_data_rising[18]),
                            .write_data_falling(write_data_falling[18]),
                            .read_data_in(dq[18]),
                            .clk90(clk90),
			//XST_REMOVECOMMENT .clk270(clk270),
                            .write_en_val(write_en_val),
                            .reset(reset270_r)
                           ); 
                           
ddr_dq_iob  ddr_dq_iob19( 
                            .ddr_dq_inout(ddr_dq[19]),
                            .write_data_rising(write_data_rising[19]),
                            .write_data_falling(write_data_falling[19]),
                            .read_data_in(dq[19]),
                            .clk90(clk90),
			//XST_REMOVECOMMENT .clk270(clk270),
                            .write_en_val(write_en_val),
                            .reset(reset270_r)
                           ); 
                           
ddr_dq_iob  ddr_dq_iob20( 
                            .ddr_dq_inout(ddr_dq[20]),
                            .write_data_rising(write_data_rising[20]),
                            .write_data_falling(write_data_falling[20]),
                            .read_data_in(dq[20]),
                            .clk90(clk90),
			//XST_REMOVECOMMENT .clk270(clk270),
                            .write_en_val(write_en_val),
                            .reset(reset270_r)
                           ); 
                          

ddr_dq_iob  ddr_dq_iob21( 
                            .ddr_dq_inout(ddr_dq[21]),
                            .write_data_rising(write_data_rising[21]),
                            .write_data_falling(write_data_falling[21]),
                            .read_data_in(dq[21]),
                            .clk90(clk90),
			//XST_REMOVECOMMENT .clk270(clk270),
                            .write_en_val(write_en_val),
                            .reset(reset270_r)
                           ); 
                           
ddr_dq_iob  ddr_dq_iob22( 
                            .ddr_dq_inout(ddr_dq[22]),
                            .write_data_rising(write_data_rising[22]),
                            .write_data_falling(write_data_falling[22]),
                            .read_data_in(dq[22]),
                            .clk90(clk90),
			//XST_REMOVECOMMENT .clk270(clk270),
                            .write_en_val(write_en_val),
                            .reset(reset270_r)
                           ); 
                           
ddr_dq_iob  ddr_dq_iob23( 
                            .ddr_dq_inout(ddr_dq[23]),
                            .write_data_rising(write_data_rising[23]),
                            .write_data_falling(write_data_falling[23]),
                            .read_data_in(dq[23]),
                            .clk90(clk90),
			//XST_REMOVECOMMENT .clk270(clk270),
                            .write_en_val(write_en_val),
                            .reset(reset270_r)
                           ); 

ddr_dq_iob  ddr_dq_iob24( 
                            .ddr_dq_inout(ddr_dq[24]),
                            .write_data_rising(write_data_rising[24]),
                            .write_data_falling(write_data_falling[24]),
                            .read_data_in(dq[24]),
                            .clk90(clk90),
			//XST_REMOVECOMMENT .clk270(clk270),
                            .write_en_val(write_en_val),
                            .reset(reset270_r)
                           ); 

ddr_dq_iob  ddr_dq_iob25( 
                            .ddr_dq_inout(ddr_dq[25]),
                            .write_data_rising(write_data_rising[25]),
                            .write_data_falling(write_data_falling[25]),
                            .read_data_in(dq[25]),
                            .clk90(clk90),
			//XST_REMOVECOMMENT .clk270(clk270),
                            .write_en_val(write_en_val),
                            .reset(reset270_r)
                           ); 


ddr_dq_iob  ddr_dq_iob26( 
                            .ddr_dq_inout(ddr_dq[26]),
                            .write_data_rising(write_data_rising[26]),
                            .write_data_falling(write_data_falling[26]),
                            .read_data_in(dq[26]),
                            .clk90(clk90),
			//XST_REMOVECOMMENT .clk270(clk270),
                            .write_en_val(write_en_val),
                            .reset(reset270_r)
                           ); 

ddr_dq_iob  ddr_dq_iob27( 
                            .ddr_dq_inout(ddr_dq[27]),
                            .write_data_rising(write_data_rising[27]),
                            .write_data_falling(write_data_falling[27]),
                            .read_data_in(dq[27]),
                            .clk90(clk90),
			//XST_REMOVECOMMENT .clk270(clk270),
                            .write_en_val(write_en_val),
                            .reset(reset270_r)
                           ); 
                              
ddr_dq_iob  ddr_dq_iob28( 
                            .ddr_dq_inout(ddr_dq[28]),
                            .write_data_rising(write_data_rising[28]),
                            .write_data_falling(write_data_falling[28]),
                            .read_data_in(dq[28]),
                            .clk90(clk90),
			//XST_REMOVECOMMENT .clk270(clk270),
                            .write_en_val(write_en_val),
                            .reset(reset270_r)
                           ); 
                              
ddr_dq_iob  ddr_dq_iob29( 
                            .ddr_dq_inout(ddr_dq[29]),
                            .write_data_rising(write_data_rising[29]),
                            .write_data_falling(write_data_falling[29]),
                            .read_data_in(dq[29]),
                            .clk90(clk90),
			//XST_REMOVECOMMENT .clk270(clk270),
                            .write_en_val(write_en_val),
                            .reset(reset270_r)
                           ); 
                           
ddr_dq_iob  ddr_dq_iob30( 
                            .ddr_dq_inout(ddr_dq[30]),
                            .write_data_rising(write_data_rising[30]),
                            .write_data_falling(write_data_falling[30]),
                            .read_data_in(dq[30]),
                            .clk90(clk90),
			//XST_REMOVECOMMENT .clk270(clk270),
                            .write_en_val(write_en_val),
                            .reset(reset270_r)
                           ); 
                           
ddr_dq_iob  ddr_dq_iob31( 
                            .ddr_dq_inout(ddr_dq[31]),
                            .write_data_rising(write_data_rising[31]),
                            .write_data_falling(write_data_falling[31]),
                            .read_data_in(dq[31]),
                            .clk90(clk90),
			//XST_REMOVECOMMENT .clk270(clk270),
                            .write_en_val(write_en_val),
                            .reset(reset270_r)
                           );                            


//***********************************************************************
//  DM IOB instantiations
//***********************************************************************  


ddr1_dm_32bit ddr1_dm0 (
                    .ddr_dm(ddr_dm),
			//XST_REMOVECOMMENT .clk270(clk270),
                    .mask_falling(data_mask_f),
                    .mask_rising(data_mask_r),
                    .clk90(clk90)
                   );    

                                                                                                                                                                                                                                                                         
                                                                                                                                                                                                                                                                        
                                                                                                                                                                                                                                                                      
                                                                                                                                                                                                                                                                    
endmodule