infrastructure.v

来自「XILINX memory interface generator. XILI」· Verilog 代码 · 共 58 行

  `timescale 1ns/100ps
module infrastructure (
       sys_rst,
       clk_int,     
       rst_calib1, 
       delay_sel_val,      
       delay_sel_val1_val);

  
input        sys_rst;
input        clk_int;
input        rst_calib1; 
input [4:0] delay_sel_val;      
output       [4:0]delay_sel_val1_val;   

wire user_rst;
wire clk_int; 
wire clk90_int;
wire dcm_lock; 

wire [4:0]delay_sel_val;    
wire [4:0]delay_sel_val1;   
reg [4:0]delay_sel_val1_r; 
reg rst_calib1_r1;
reg rst_calib1_r2;

wire vcc;

wire clk_int_val1;
wire clk_int_val2;
wire clk90_int_val1;
wire clk90_int_val2;


assign delay_sel_val1_val = delay_sel_val1;
assign delay_sel_val1 = (rst_calib1 == 1'b0 && rst_calib1_r2 == 1'b0) ? delay_sel_val :delay_sel_val1_r;

always@(posedge clk_int)
begin
   if (sys_rst == 1'b1)
     begin  
     delay_sel_val1_r <= 5'b00000;
     rst_calib1_r1    <= 1'b0;
     rst_calib1_r2    <= 1'b0;
     end
   else
     begin
     delay_sel_val1_r <= delay_sel_val1;
     rst_calib1_r1    <= rst_calib1;
     rst_calib1_r2    <= rst_calib1_r1;
     end
end

endmodule